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Merge pull request #5357 from rocallahan/builtin-ff

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Instead of using `builtin_ff_cell_types()` directly, go through a method `Cell::is_builtin_ff()`
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Emil J 2025-09-17 11:37:16 +02:00 • committed by GitHub
commit 73e47ac3fe
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GPG key ID: B5690EEEBB952194
32 changed files with 61 additions and 51 deletions
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4
passes/techmap/abc.cc
View file

@ -373,7 +373,7 @@ void AbcModuleState::mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig)
bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, bool keepff)
{
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (cell->is_builtin_ff()) {
FfData ff(&initvals, cell);
gate_type_t type = G(FF);
if (!ff.has_clk)
@ -2427,7 +2427,7 @@ struct AbcPass : public Pass {
}
}
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);

2
passes/techmap/abc9_ops.cc
View file

@ -224,7 +224,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
}
else if (derived_module->get_bool_attribute(ID::abc9_box)) {
for (auto derived_cell : derived_module->cells())
if (derived_cell->is_mem_cell() || RTLIL::builtin_ff_cell_types().count(derived_cell->type)) {
if (derived_cell->is_mem_cell() || derived_cell->is_builtin_ff()) {
derived_module->set_bool_attribute(ID::abc9_box, false);
derived_module->set_bool_attribute(ID::abc9_bypass);
break;

2
passes/techmap/clockgate.cc
View file

@ -333,7 +333,7 @@ struct ClockgatePass : public Pass {
int gated_flop_count = 0;
for (auto module : design->selected_unboxed_whole_modules()) {
for (auto cell : module->cells()) {
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(nullptr, cell);

4
passes/techmap/dfflegalize.cc
View file

@ -1196,7 +1196,7 @@ unrecognized:
srst_used.clear();
for (auto cell : module->cells()) {
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);
@ -1208,7 +1208,7 @@ unrecognized:
}
for (auto cell : module->selected_cells())
{
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);
legalize_ff(ff);

2
passes/techmap/dffunmap.cc
View file

@ -74,7 +74,7 @@ struct DffunmapPass : public Pass {
for (auto cell : mod->selected_cells())
{
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);

2
passes/techmap/zinit.cc
View file

@ -63,7 +63,7 @@ struct ZinitPass : public Pass {
for (auto cell : module->selected_cells())
{
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);