diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index b03639b8d..aea29f710 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -970,7 +970,7 @@ void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, b std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && RTLIL::builtin_ff_cell_types().count(cell->type) && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) + if (!norename && cell->name[0] == '$' && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) { RTLIL::SigSpec sig = cell->getPort(ID::Q); if (GetSize(sig) != 1 || sig.is_fully_const()) @@ -1498,7 +1498,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) { FfData ff(nullptr, cell); @@ -1976,7 +1976,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } - if (siminit && RTLIL::builtin_ff_cell_types().count(cell->type) && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) { + if (siminit && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) { std::stringstream ss; dump_reg_init(ss, cell->getPort(ID::Q)); if (!ss.str().empty()) { @@ -2334,7 +2334,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) continue; } - if (!RTLIL::builtin_ff_cell_types().count(cell->type) || !cell->hasPort(ID::Q) || cell->type.in(ID($ff), ID($_FF_))) + if (!cell->is_builtin_ff() || !cell->hasPort(ID::Q) || cell->type.in(ID($ff), ID($_FF_))) continue; RTLIL::SigSpec sig = cell->getPort(ID::Q); diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 8e52d0380..c39ced95a 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -447,7 +447,7 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return true; } - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { ff_op(this, cell); return true; } diff --git a/kernel/cost.cc b/kernel/cost.cc index 985220f14..29787fa52 100644 --- a/kernel/cost.cc +++ b/kernel/cost.cc @@ -145,7 +145,7 @@ unsigned int CellCosts::get(RTLIL::Cell *cell) if (design_ && design_->module(cell->type) && cell->parameters.empty()) { log_debug("%s is a module, recurse\n", cell->name.c_str()); return get(design_->module(cell->type)); - } else if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + } else if (cell->is_builtin_ff()) { log_assert(cell->hasPort(ID::Q) && "Weird flip flop"); log_debug("%s is ff\n", cell->name.c_str()); return cell->getParam(ID::WIDTH).as_int(); diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc index 632cba05c..709549e4d 100644 --- a/kernel/ffmerge.cc +++ b/kernel/ffmerge.cc @@ -335,7 +335,7 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_) } for (auto cell : module->cells()) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { if (cell->hasPort(ID::D)) { SigSpec d = (*sigmap)(cell->getPort(ID::D)); for (int i = 0; i < GetSize(d); i++) diff --git a/kernel/functional.cc b/kernel/functional.cc index 75c9b580b..2a1bf598a 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -605,7 +605,7 @@ private: } Node node = handle_memory(mem); factory.update_pending(cell_outputs.at({cell, ID(RD_DATA)}), node); - } else if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + } else if (cell->is_builtin_ff()) { FfData ff(&ff_initvals, cell); if (!ff.has_gclk) log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. " diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 586262f97..2d29dab9f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -87,7 +87,7 @@ static_assert(check_well_known_id_order()); dict RTLIL::constpad; -const pool &RTLIL::builtin_ff_cell_types() { +static const pool &builtin_ff_cell_types_internal() { static const pool res = { ID($sr), ID($ff), @@ -238,6 +238,10 @@ const pool &RTLIL::builtin_ff_cell_types() { return res; } +const pool &RTLIL::builtin_ff_cell_types() { + return builtin_ff_cell_types_internal(); +} + #define check(condition) log_assert(condition && "malformed Const union") const Const::bitvectype& Const::get_bits() const { @@ -4497,6 +4501,10 @@ bool RTLIL::Cell::is_mem_cell() const return type.in(ID($mem), ID($mem_v2)) || has_memid(); } +bool RTLIL::Cell::is_builtin_ff() const { + return builtin_ff_cell_types_internal().count(type) > 0; +} + RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit) { wire = bit.wire; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6b4bc0c7d..2d7bf9a9c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -556,6 +556,7 @@ template <> struct IDMacroHelper<-1> { namespace RTLIL { extern dict constpad; + [[deprecated("Call cell->is_builtin_ff() instead")]] const pool &builtin_ff_cell_types(); static inline std::string escape_id(const std::string &str) { @@ -2147,6 +2148,7 @@ public: bool has_memid() const; bool is_mem_cell() const; + bool is_builtin_ff() const; }; struct RTLIL::CaseRule : public RTLIL::AttrObject diff --git a/kernel/satgen.cc b/kernel/satgen.cc index 7885eccf8..f2c1e00c2 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -1202,7 +1202,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) return true; } - if (timestep > 0 && (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit))) + if (timestep > 0 && (cell->is_builtin_ff() || cell->type == ID($anyinit))) { FfData ff(nullptr, cell); diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 9f72d90f7..b7a5feb57 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -285,7 +285,7 @@ struct CheckPass : public Pass { } if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \ - || RTLIL::builtin_ff_cell_types().count(cell->type)) { + || cell->is_builtin_ff()) { if (!edges_db.add_edges_from_cell(cell)) coarsened_cells.insert(cell); } @@ -426,7 +426,7 @@ struct CheckPass : public Pass { { for (auto cell : module->cells()) { - if (RTLIL::builtin_ff_cell_types().count(cell->type) == 0) + if (cell->is_builtin_ff() == 0) continue; for (auto bit : sigmap(cell->getPort(ID::Q))) diff --git a/passes/cmds/clean_zerowidth.cc b/passes/cmds/clean_zerowidth.cc index 021726450..d48d3a958 100644 --- a/passes/cmds/clean_zerowidth.cc +++ b/passes/cmds/clean_zerowidth.cc @@ -73,7 +73,7 @@ struct CleanZeroWidthPass : public Pass { cell->unsetPort(it.first); } } - } else if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + } else if (cell->is_builtin_ff()) { // Coarse FF cells: remove if WIDTH == 0 (no outputs). // This will also trigger on fine cells, so use the Q port // width instead of actual WIDTH parameter. diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index 5d9756ca0..0a306d113 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -430,7 +430,7 @@ struct DftTagWorker { return; } - if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + if (cell->is_builtin_ff() || cell->type == ID($anyinit)) { FfData ff(&initvals, cell); if (ff.has_clk || ff.has_gclk) @@ -686,7 +686,7 @@ struct DftTagWorker { return; } - if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + if (cell->is_builtin_ff() || cell->type == ID($anyinit)) { FfData ff(&initvals, cell); // TODO handle some more variants if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) { diff --git a/passes/cmds/future.cc b/passes/cmds/future.cc index 5dcf46bcf..81cc86bff 100644 --- a/passes/cmds/future.cc +++ b/passes/cmds/future.cc @@ -85,7 +85,7 @@ struct FutureWorker { if (found_driver->second.size() > 1) log_error("Found multiple drivers for future_ff target signal %s\n", log_signal(bit)); auto driver = *found_driver->second.begin(); - if (!RTLIL::builtin_ff_cell_types().count(driver.cell->type) && driver.cell->type != ID($anyinit)) + if (!driver.cell->is_builtin_ff() && driver.cell->type != ID($anyinit)) log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), log_id(driver.cell->type)); FfData ff(&initvals, driver.cell); diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 6d3e30561..5d2ccfcc8 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -364,7 +364,7 @@ struct SetundefPass : public Pass { for (auto cell : module->cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; for (auto bit : sigmap(cell->getPort(ID::Q))) diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc index b878050da..ce9c628f4 100644 --- a/passes/cmds/timeest.cc +++ b/passes/cmds/timeest.cc @@ -88,7 +88,7 @@ struct EstimateSta { for (auto cell : m->cells()) { SigSpec launch, sample; - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { // collect launch and sample points for FF cell FfData ff(nullptr, cell); if (!ff.has_clk) { diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc index 8b2e7ae08..7291bb859 100644 --- a/passes/cmds/xprop.cc +++ b/passes/cmds/xprop.cc @@ -302,7 +302,7 @@ struct XpropWorker return; } - if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + if (cell->is_builtin_ff() || cell->type == ID($anyinit)) { FfData ff(&initvals, cell); if (cell->type != ID($anyinit)) @@ -853,7 +853,7 @@ struct XpropWorker return; } - if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + if (cell->is_builtin_ff() || cell->type == ID($anyinit)) { FfData ff(&initvals, cell); if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) { diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index 1995be3cd..e1a3a7990 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -56,7 +56,7 @@ struct EquivInductWorker for (auto cell : cells) { if (!satgen.importCell(cell, step) && !cell_warn_cache.count(cell)) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) log_warning("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type)); else log_warning("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type)); diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index 9e3076077..97f95ac63 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -93,7 +93,7 @@ struct EquivSimpleWorker for (auto &conn : cell->connections()) if (yosys_celltypes.cell_input(cell->type, conn.first)) for (auto bit : model.sigmap(conn.second)) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { if (!conn.first.in(ID::CLK, ID::C)) next_seed.insert(bit); } else @@ -231,7 +231,7 @@ struct EquivSimpleWorker static void report_missing_model(Cell* cell) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) log_cmd_error("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type)); else log_cmd_error("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type)); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index b9df09ea6..d9bd4c027 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -206,7 +206,7 @@ void rmunused_module_cells(Module *module, bool verbose) if (verbose) log_debug(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str()); module->design->scratchpad_set_bool("opt.did_something", true); - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) ffinit.remove_init(cell->getPort(ID::Q)); module->remove(cell); count_rm_cells++; diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index a364539e4..04bcec835 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -89,7 +89,7 @@ struct OptDffWorker } } - if (module->design->selected(module, cell) && RTLIL::builtin_ff_cell_types().count(cell->type)) + if (module->design->selected(module, cell) && cell->is_builtin_ff()) dff_cells.push_back(cell); } @@ -802,7 +802,7 @@ struct OptDffWorker bool did_something = false; for (auto cell : module->selected_cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc index 882221e56..42d6da49b 100644 --- a/passes/opt/opt_ffinv.cc +++ b/passes/opt/opt_ffinv.cc @@ -209,7 +209,7 @@ struct OptFfInvWorker std::vector ffs; for (Cell *cell : module->selected_cells()) - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) ffs.push_back(cell); for (Cell *cell : ffs) { diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index fbfdb9b63..1cb499740 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -110,7 +110,7 @@ struct OptMergeWorker comm.eat(hash_ops>::hash(port, assign_map(sig))); } h = comm.hash_into(h); - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) h = initvals(cell->getPort(ID::Q)).hash_into(h); } return h; @@ -153,7 +153,7 @@ struct OptMergeWorker for (const auto &it : cell1->connections_) { if (cell1->output(it.first)) { - if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell1->type)) { + if (it.first == ID::Q && cell1->is_builtin_ff()) { // For the 'Q' output of state elements, // use the (* init *) attribute value conn1[it.first] = initvals(it.second); @@ -201,7 +201,7 @@ struct OptMergeWorker bool has_dont_care_initval(const RTLIL::Cell *cell) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) return false; return !initvals(cell->getPort(ID::Q)).is_fully_def(); diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index e86a78d81..eb3b154b2 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -129,7 +129,7 @@ struct Async2syncPass : public Pass { continue; } - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index db1eaad4b..dd94dd0d7 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -275,7 +275,7 @@ struct Clk2fflogicPass : public Pass { continue; } - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index 2d31822c4..505526c14 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -118,7 +118,7 @@ struct FmcombineWorker Cell *gold = import_prim_cell(cell, "_gold"); Cell *gate = import_prim_cell(cell, "_gate"); if (opts.initeq) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { SigSpec gold_q = gold->getPort(ID::Q); SigSpec gate_q = gate->getPort(ID::Q); SigSpec en = module->Initstate(NEW_ID); diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc index c0b0cfc15..452e0e59b 100644 --- a/passes/sat/formalff.cc +++ b/passes/sat/formalff.cc @@ -92,7 +92,7 @@ struct InitValWorker ModWalker::PortBit portbit = *portbits.begin(); RTLIL::Cell *cell = portbit.cell; - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) { FfData ff(&initvals, cell); @@ -224,7 +224,7 @@ struct InitValWorker for (auto portbit : portbits) { RTLIL::Cell *cell = portbit.cell; - if (!cell->type.in(ID($mux), ID($and), ID($or), ID($mem_v2)) && !RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (!cell->type.in(ID($mux), ID($and), ID($or), ID($mem_v2)) && !cell->is_builtin_ff()) { return true; } } @@ -232,7 +232,7 @@ struct InitValWorker for (auto portbit : portbits) { RTLIL::Cell *cell = portbit.cell; - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) { FfData ff(&initvals, cell); if (ff.has_aload || ff.has_sr || ff.has_arst || ff.has_gclk || !ff.has_clk) @@ -641,7 +641,7 @@ struct FormalFfPass : public Pass { pool input_bits; pool> input_clk_bits; for (auto cell : module->selected_cells()) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { FfData ff(&initvals, cell); if (!ff.has_clk) continue; @@ -743,7 +743,7 @@ struct FormalFfPass : public Pass { auto gate_driver = *found->second.begin(); - if (!RTLIL::builtin_ff_cell_types().count(gate_driver.cell->type)) { + if (!gate_driver.cell->is_builtin_ff()) { log_debug("non FF driver for gate enable %s.%s of gated clk bit %s.%s\n", log_id(module), log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk))); continue; @@ -784,7 +784,7 @@ struct FormalFfPass : public Pass { log_debug("rewriting cell %s.%s (%s)\n", log_id(module), log_id(clocked_cell), log_id(clocked_cell->type)); - if (RTLIL::builtin_ff_cell_types().count(clocked_cell->type)) { + if (clocked_cell->is_builtin_ff()) { FfData ff(&initvals, clocked_cell); log_assert(ff.has_clk); @@ -836,7 +836,7 @@ struct FormalFfPass : public Pass { for (auto cell : module->selected_cells()) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) { FfData ff(&worker.initvals, cell); if (ff.has_aload || ff.has_sr || ff.has_arst || ff.val_init.is_fully_def()) @@ -883,7 +883,7 @@ struct FormalFfPass : public Pass { continue; } - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 1b653a218..fac7bd744 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -308,7 +308,7 @@ struct SimInstance } } - if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + if (cell->is_builtin_ff() || cell->type == ID($anyinit)) { FfData ff_data(nullptr, cell); ff_state_t ff; ff.past_d = Const(State::Sx, ff_data.width); @@ -1017,7 +1017,7 @@ struct SimInstance dict registers; for (auto cell : module->cells()) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { FfData ff_data(nullptr, cell); SigSpec q = sigmap(ff_data.sig_q); if (q.is_wire() && signal_database.count(q.as_wire()) != 0) { diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 9cd02b455..c17f85afd 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -373,7 +373,7 @@ void AbcModuleState::mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig) bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, bool keepff) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { FfData ff(&initvals, cell); gate_type_t type = G(FF); if (!ff.has_clk) @@ -2427,7 +2427,7 @@ struct AbcPass : public Pass { } } - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 069b94204..9a9f7dcb5 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -224,7 +224,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) } else if (derived_module->get_bool_attribute(ID::abc9_box)) { for (auto derived_cell : derived_module->cells()) - if (derived_cell->is_mem_cell() || RTLIL::builtin_ff_cell_types().count(derived_cell->type)) { + if (derived_cell->is_mem_cell() || derived_cell->is_builtin_ff()) { derived_module->set_bool_attribute(ID::abc9_box, false); derived_module->set_bool_attribute(ID::abc9_bypass); break; diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index b834b8f35..f4e0b0f03 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -333,7 +333,7 @@ struct ClockgatePass : public Pass { int gated_flop_count = 0; for (auto module : design->selected_unboxed_whole_modules()) { for (auto cell : module->cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(nullptr, cell); diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 5a622c611..dc29750c8 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -1196,7 +1196,7 @@ unrecognized: srst_used.clear(); for (auto cell : module->cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); @@ -1208,7 +1208,7 @@ unrecognized: } for (auto cell : module->selected_cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); legalize_ff(ff); diff --git a/passes/techmap/dffunmap.cc b/passes/techmap/dffunmap.cc index 8703bf1a0..020597c4b 100644 --- a/passes/techmap/dffunmap.cc +++ b/passes/techmap/dffunmap.cc @@ -74,7 +74,7 @@ struct DffunmapPass : public Pass { for (auto cell : mod->selected_cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc index 38936e64d..809651ebd 100644 --- a/passes/techmap/zinit.cc +++ b/passes/techmap/zinit.cc @@ -63,7 +63,7 @@ struct ZinitPass : public Pass { for (auto cell : module->selected_cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell);