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Merge pull request #5357 from rocallahan/builtin-ff

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Instead of using `builtin_ff_cell_types()` directly, go through a method `Cell::is_builtin_ff()`
This commit is contained in:
Emil J 2025-09-17 11:37:16 +02:00 • committed by GitHub
commit 73e47ac3fe
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GPG key ID: B5690EEEBB952194
32 changed files with 61 additions and 51 deletions
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2
passes/sat/async2sync.cc
View file

@ -129,7 +129,7 @@ struct Async2syncPass : public Pass {
continue;
}
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);

2
passes/sat/clk2fflogic.cc
View file

@ -275,7 +275,7 @@ struct Clk2fflogicPass : public Pass {
continue;
}
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);

2
passes/sat/fmcombine.cc
View file

@ -118,7 +118,7 @@ struct FmcombineWorker
Cell *gold = import_prim_cell(cell, "_gold");
Cell *gate = import_prim_cell(cell, "_gate");
if (opts.initeq) {
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (cell->is_builtin_ff()) {
SigSpec gold_q = gold->getPort(ID::Q);
SigSpec gate_q = gate->getPort(ID::Q);
SigSpec en = module->Initstate(NEW_ID);

16
passes/sat/formalff.cc
View file

@ -92,7 +92,7 @@ struct InitValWorker
ModWalker::PortBit portbit = *portbits.begin();
RTLIL::Cell *cell = portbit.cell;
if (RTLIL::builtin_ff_cell_types().count(cell->type))
if (cell->is_builtin_ff())
{
FfData ff(&initvals, cell);
@ -224,7 +224,7 @@ struct InitValWorker
for (auto portbit : portbits) {
RTLIL::Cell *cell = portbit.cell;
if (!cell->type.in(ID($mux), ID($and), ID($or), ID($mem_v2)) && !RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (!cell->type.in(ID($mux), ID($and), ID($or), ID($mem_v2)) && !cell->is_builtin_ff()) {
return true;
}
}
@ -232,7 +232,7 @@ struct InitValWorker
for (auto portbit : portbits)
{
RTLIL::Cell *cell = portbit.cell;
if (RTLIL::builtin_ff_cell_types().count(cell->type))
if (cell->is_builtin_ff())
{
FfData ff(&initvals, cell);
if (ff.has_aload || ff.has_sr || ff.has_arst || ff.has_gclk || !ff.has_clk)
@ -641,7 +641,7 @@ struct FormalFfPass : public Pass {
pool<SigBit> input_bits;
pool<pair<SigBit, bool>> input_clk_bits;
for (auto cell : module->selected_cells()) {
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (cell->is_builtin_ff()) {
FfData ff(&initvals, cell);
if (!ff.has_clk)
continue;
@ -743,7 +743,7 @@ struct FormalFfPass : public Pass {
auto gate_driver = *found->second.begin();
if (!RTLIL::builtin_ff_cell_types().count(gate_driver.cell->type)) {
if (!gate_driver.cell->is_builtin_ff()) {
log_debug("non FF driver for gate enable %s.%s of gated clk bit %s.%s\n", log_id(module),
log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk)));
continue;
@ -784,7 +784,7 @@ struct FormalFfPass : public Pass {
log_debug("rewriting cell %s.%s (%s)\n", log_id(module), log_id(clocked_cell),
log_id(clocked_cell->type));
if (RTLIL::builtin_ff_cell_types().count(clocked_cell->type)) {
if (clocked_cell->is_builtin_ff()) {
FfData ff(&initvals, clocked_cell);
log_assert(ff.has_clk);
@ -836,7 +836,7 @@ struct FormalFfPass : public Pass {
for (auto cell : module->selected_cells())
{
if (RTLIL::builtin_ff_cell_types().count(cell->type))
if (cell->is_builtin_ff())
{
FfData ff(&worker.initvals, cell);
if (ff.has_aload || ff.has_sr || ff.has_arst || ff.val_init.is_fully_def())
@ -883,7 +883,7 @@ struct FormalFfPass : public Pass {
continue;
}
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
if (!cell->is_builtin_ff())
continue;
FfData ff(&initvals, cell);

4
passes/sat/sim.cc
View file

@ -308,7 +308,7 @@ struct SimInstance
}
}
if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
if (cell->is_builtin_ff() || cell->type == ID($anyinit)) {
FfData ff_data(nullptr, cell);
ff_state_t ff;
ff.past_d = Const(State::Sx, ff_data.width);
@ -1017,7 +1017,7 @@ struct SimInstance
dict<Wire*,bool> registers;
for (auto cell : module->cells())
{
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
if (cell->is_builtin_ff()) {
FfData ff_data(nullptr, cell);
SigSpec q = sigmap(ff_data.sig_q);
if (q.is_wire() && signal_database.count(q.as_wire()) != 0) {