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Modified errors into warnings

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No longer false warnings for memories and assertions
This commit is contained in:
Udi Finkelstein 2018-06-05 17:44:24 +03:00 • committed by Unknown
parent 80d9d15f1c
commit 73d426bc87
5 changed files with 79 additions and 11 deletions
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42
tests/various/reg_wire_error.sv
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@ -2,11 +2,13 @@ module sub_mod(input i_in, output o_out);
assign o_out = i_in;
endmodule
module test(i_clk, i_reg, o_reg, o_wire);
module test(i_clk, i, i_reg, o_reg, o_wire, o_mr, o_mw, o_ml);
input i_clk;
input i;
input i_reg;
output o_reg;
output o_wire;
output o_mr, o_mw, o_ml;
// Enable this to see how it doesn't fail on yosys although it should
//reg o_wire;
@ -15,12 +17,12 @@ logic o_wire;
// Enable this to see how it doesn't fail on yosys although it should
//reg i_reg;
// Disable this to see how it doesn't fail on yosys although it should
reg o_reg;
//reg o_reg;
logic l_reg;
// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
//assign l_reg = !o_reg;
assign l_reg = !o_reg;
initial o_reg = 1'b0;
always @(posedge i_clk)
begin
@ -30,11 +32,43 @@ end
assign o_wire = !o_reg;
// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
//assign l_reg = !o_reg;
assign l_reg = !o_reg;
sub_mod sm_inst (
.i_in(1'b1),
.o_out(o_reg)
);
wire mw1[0:1];
wire mw2[0:1];
wire mw3[0:1];
reg mr1[0:1];
reg mr2[0:1];
reg mr3[0:1];
logic ml1[0:1];
logic ml2[0:1];
logic ml3[0:1];
assign o_mw = mw1[i];
assign o_mr = mr1[i];
assign o_ml = ml1[i];
assign mw1[1] = 1'b1;
//assign mr1[1] = 1'b1;
assign ml1[1] = 1'b1;
always @(posedge i_clk)
begin
mr2[0] = 1'b0;
mw2[0] = 1'b0;
ml2[0] = 1'b0;
end
always @(posedge i_clk)
begin
mr3[0] <= 1'b0;
mw3[0] <= 1'b0;
ml3[0] <= 1'b0;
end
endmodule