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Modified errors into warnings

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No longer false warnings for memories and assertions
This commit is contained in:
Udi Finkelstein 2018-06-05 17:44:24 +03:00 • committed by Unknown
parent 80d9d15f1c
commit 73d426bc87
5 changed files with 79 additions and 11 deletions
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1
frontends/verilog/verilog_parser.y
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@ -548,6 +548,7 @@ task_func_decl:
AstNode *outreg = new AstNode(AST_WIRE);
outreg->str = *$6;
outreg->is_signed = $4;
outreg->is_reg = true;
if ($5 != NULL) {
outreg->children.push_back($5);
outreg->is_signed = $4 || $5->is_signed;