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rtlil: Module::clone attaches to source design; callers use clone(dst)

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This commit is contained in:
Emil J. Tywoniak 2026-06-05 21:15:24 +02:00
parent 8f8a07efee
commit 734593e12d
4 changed files with 7 additions and 5 deletions
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2
passes/techmap/techmap.cc
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@ -1225,7 +1225,7 @@ struct TechmapPass : public Pass {
}
for (auto mod : saved_designs.at(fn.substr(1))->modules())
if (!map->module(mod->name))
map->add(mod->clone());
mod->clone(map);
} else {
Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend));
}