From 734593e12d0dc48f7c7701a3c0985df8218e6569 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 5 Jun 2026 21:15:24 +0200
Subject: [PATCH] rtlil: Module::clone attaches to source design; callers use
 clone(dst)

---
 kernel/rtlil.cc           | 2 ++
 passes/cmds/bugpoint.cc   | 6 +++---
 passes/techmap/extract.cc | 2 +-
 passes/techmap/techmap.cc | 2 +-
 4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index c15a54015..7ecebfb89 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3251,6 +3251,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons
 RTLIL::Module *RTLIL::Module::clone() const
 {
 	RTLIL::Module *new_mod = new RTLIL::Module;
+	new_mod->design = design;
 	new_mod->name = name;
 	cloneInto(new_mod);
 	return new_mod;
@@ -3259,6 +3260,7 @@ RTLIL::Module *RTLIL::Module::clone() const
 RTLIL::Module *RTLIL::Module::clone(RTLIL::Design *dst, bool src_id_verbatim) const
 {
 	RTLIL::Module *new_mod = new RTLIL::Module;
+	new_mod->design = dst;
 	new_mod->name = name;
 	dst->add(new_mod);
 	cloneInto(new_mod, src_id_verbatim);
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index 6a630ca4b..4f6589fc3 100644
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -183,7 +183,7 @@ struct BugpointPass : public Pass {
 
 		RTLIL::Design *design_copy = new RTLIL::Design;
 		for (auto module : design->modules())
-			design_copy->add(module->clone());
+			module->clone(design_copy);
 		Pass::call(design_copy, "proc_clean -quiet");
 		Pass::call(design_copy, "clean -purge");
 
@@ -196,7 +196,7 @@ struct BugpointPass : public Pass {
 	{
 		RTLIL::Design *design_copy = new RTLIL::Design;
 		for (auto module : design->modules())
-			design_copy->add(module->clone());
+			module->clone(design_copy);
 
 		int index = 0;
 		if (modules)
@@ -678,7 +678,7 @@ struct BugpointPass : public Pass {
 			Pass::call(design, "design -reset");
 			crashing_design = clean_design(crashing_design, clean, /*do_delete=*/true);
 			for (auto module : crashing_design->modules())
-				design->add(module->clone());
+				module->clone(design);
 			delete crashing_design;
 		}
 
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index f63123a23..466bef68a 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -596,7 +596,7 @@ struct ExtractPass : public Pass {
 					}
 					for (auto mod : saved_designs.at(filename.substr(1))->modules())
 						if (!map->has(mod->name))
-							map->add(mod->clone());
+							mod->clone(map);
 				}
 				else
 				{
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 66d154c07..0b5ef497b 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1225,7 +1225,7 @@ struct TechmapPass : public Pass {
 					}
 					for (auto mod : saved_designs.at(fn.substr(1))->modules())
 						if (!map->module(mod->name))
-							map->add(mod->clone());
+							mod->clone(map);
 				} else {
 					Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend));
 				}