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Add muxcover changes
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1
Makefile
1
Makefile
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@ -729,6 +729,7 @@ OBJS += passes/techmap/alumacc.o
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OBJS += passes/techmap/pmuxtree.o
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OBJS += passes/techmap/bmuxmap.o
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OBJS += passes/techmap/demuxmap.o
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OBJS += passes/techmap/muxcover.o
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OBJS += passes/techmap/aigmap.o
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include $(YOSYS_SRC)/passes/hierarchy/Makefile.inc
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@ -505,77 +505,58 @@ struct MuxcoverWorker
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for (auto inbit : mux.inputs)
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implement_best_cover(tree, inbit, count_muxes_by_type);
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for (auto selbit : mux.selects)
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implement_decode_mux(selbit);
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// for (auto selbit : mux.selects)
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// implement_decode_mux(selbit);
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if (GetSize(mux.inputs) == 0)
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return;
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// SILIMATE: For cell naming
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Cell *cell = tree.muxes[tree.root];
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Module *module = cell->module;
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if (GetSize(mux.inputs) == 2) {
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count_muxes_by_type[0]++;
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Cell *cell = module->addCell(NEW_ID, ID($_MUX_));
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cell->setPort(ID::A, mux.inputs[0]);
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cell->setPort(ID::B, mux.inputs[1]);
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cell->setPort(ID::S, mux.selects[0]);
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cell->setPort(ID::Y, bit);
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Cell *new_cell = module->addCell(NEW_ID2_SUFFIX("muxcover"), ID($mux));
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new_cell->setPort(ID::A, mux.inputs[0]);
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new_cell->setPort(ID::B, mux.inputs[1]);
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new_cell->setPort(ID::S, mux.selects[0]);
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new_cell->setPort(ID::Y, bit);
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new_cell->fixup_parameters();
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new_cell->set_src_attribute(new_cell->get_src_attribute());
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return;
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}
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if (GetSize(mux.inputs) == 4) {
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count_muxes_by_type[1]++;
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Cell *cell = module->addCell(NEW_ID, ID($_MUX4_));
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cell->setPort(ID::A, mux.inputs[0]);
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cell->setPort(ID::B, mux.inputs[1]);
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cell->setPort(ID::C, mux.inputs[2]);
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cell->setPort(ID::D, mux.inputs[3]);
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cell->setPort(ID::S, mux.selects[0]);
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cell->setPort(ID::T, mux.selects[1]);
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cell->setPort(ID::Y, bit);
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Cell *new_cell = module->addCell(NEW_ID2_SUFFIX("muxcover"), ID($bmux));
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new_cell->setPort(ID::A, mux.inputs);
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new_cell->setPort(ID::S, mux.selects);
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new_cell->setPort(ID::Y, bit);
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new_cell->fixup_parameters();
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new_cell->set_src_attribute(new_cell->get_src_attribute());
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return;
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}
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if (GetSize(mux.inputs) == 8) {
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count_muxes_by_type[2]++;
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Cell *cell = module->addCell(NEW_ID, ID($_MUX8_));
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cell->setPort(ID::A, mux.inputs[0]);
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cell->setPort(ID::B, mux.inputs[1]);
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cell->setPort(ID::C, mux.inputs[2]);
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cell->setPort(ID::D, mux.inputs[3]);
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cell->setPort(ID::E, mux.inputs[4]);
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cell->setPort(ID::F, mux.inputs[5]);
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cell->setPort(ID::G, mux.inputs[6]);
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cell->setPort(ID::H, mux.inputs[7]);
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cell->setPort(ID::S, mux.selects[0]);
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cell->setPort(ID::T, mux.selects[1]);
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cell->setPort(ID::U, mux.selects[2]);
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cell->setPort(ID::Y, bit);
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Cell *new_cell = module->addCell(NEW_ID2_SUFFIX("muxcover"), ID($bmux));
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new_cell->setPort(ID::A, mux.inputs);
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new_cell->setPort(ID::S, mux.selects);
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new_cell->setPort(ID::Y, bit);
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new_cell->fixup_parameters();
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new_cell->set_src_attribute(new_cell->get_src_attribute());
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return;
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}
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if (GetSize(mux.inputs) == 16) {
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count_muxes_by_type[3]++;
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Cell *cell = module->addCell(NEW_ID, ID($_MUX16_));
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cell->setPort(ID::A, mux.inputs[0]);
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cell->setPort(ID::B, mux.inputs[1]);
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cell->setPort(ID::C, mux.inputs[2]);
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cell->setPort(ID::D, mux.inputs[3]);
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cell->setPort(ID::E, mux.inputs[4]);
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cell->setPort(ID::F, mux.inputs[5]);
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cell->setPort(ID::G, mux.inputs[6]);
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cell->setPort(ID::H, mux.inputs[7]);
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cell->setPort(ID::I, mux.inputs[8]);
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cell->setPort(ID::J, mux.inputs[9]);
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cell->setPort(ID::K, mux.inputs[10]);
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cell->setPort(ID::L, mux.inputs[11]);
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cell->setPort(ID::M, mux.inputs[12]);
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cell->setPort(ID::N, mux.inputs[13]);
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cell->setPort(ID::O, mux.inputs[14]);
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cell->setPort(ID::P, mux.inputs[15]);
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cell->setPort(ID::S, mux.selects[0]);
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cell->setPort(ID::T, mux.selects[1]);
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cell->setPort(ID::U, mux.selects[2]);
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cell->setPort(ID::V, mux.selects[3]);
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cell->setPort(ID::Y, bit);
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Cell *new_cell = module->addCell(NEW_ID2_SUFFIX("muxcover"), ID($bmux));
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new_cell->setPort(ID::A, mux.inputs);
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new_cell->setPort(ID::S, mux.selects);
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new_cell->setPort(ID::Y, bit);
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new_cell->fixup_parameters();
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new_cell->set_src_attribute(new_cell->get_src_attribute());
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return;
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}
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