From 73417368b4fdd693d1313a849d133934fbb85c32 Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Sun, 9 Mar 2025 22:08:19 -0700
Subject: [PATCH] Add muxcover changes

---
 Makefile                   |  1 +
 passes/techmap/muxcover.cc | 81 +++++++++++++++-----------------------
 2 files changed, 32 insertions(+), 50 deletions(-)

diff --git a/Makefile b/Makefile
index 624cdf478..b742e93cb 100644
--- a/Makefile
+++ b/Makefile
@@ -729,6 +729,7 @@ OBJS += passes/techmap/alumacc.o
 OBJS += passes/techmap/pmuxtree.o
 OBJS += passes/techmap/bmuxmap.o
 OBJS += passes/techmap/demuxmap.o
+OBJS += passes/techmap/muxcover.o
 OBJS += passes/techmap/aigmap.o
 
 include $(YOSYS_SRC)/passes/hierarchy/Makefile.inc
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index 2656f30ce..e4123dd73 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -505,77 +505,58 @@ struct MuxcoverWorker
 		for (auto inbit : mux.inputs)
 			implement_best_cover(tree, inbit, count_muxes_by_type);
 
-		for (auto selbit : mux.selects)
-			implement_decode_mux(selbit);
+		// for (auto selbit : mux.selects)
+		// 	implement_decode_mux(selbit);
 
 		if (GetSize(mux.inputs) == 0)
 			return;
 
+		// SILIMATE: For cell naming
+		Cell *cell = tree.muxes[tree.root];
+		Module *module = cell->module;
+
 		if (GetSize(mux.inputs) == 2) {
 			count_muxes_by_type[0]++;
-			Cell *cell = module->addCell(NEW_ID, ID($_MUX_));
-			cell->setPort(ID::A, mux.inputs[0]);
-			cell->setPort(ID::B, mux.inputs[1]);
-			cell->setPort(ID::S, mux.selects[0]);
-			cell->setPort(ID::Y, bit);
+			Cell *new_cell = module->addCell(NEW_ID2_SUFFIX("muxcover"), ID($mux));
+			new_cell->setPort(ID::A, mux.inputs[0]);
+			new_cell->setPort(ID::B, mux.inputs[1]);
+			new_cell->setPort(ID::S, mux.selects[0]);
+			new_cell->setPort(ID::Y, bit);
+			new_cell->fixup_parameters();
+			new_cell->set_src_attribute(new_cell->get_src_attribute());
 			return;
 		}
 
 		if (GetSize(mux.inputs) == 4) {
 			count_muxes_by_type[1]++;
-			Cell *cell = module->addCell(NEW_ID, ID($_MUX4_));
-			cell->setPort(ID::A, mux.inputs[0]);
-			cell->setPort(ID::B, mux.inputs[1]);
-			cell->setPort(ID::C, mux.inputs[2]);
-			cell->setPort(ID::D, mux.inputs[3]);
-			cell->setPort(ID::S, mux.selects[0]);
-			cell->setPort(ID::T, mux.selects[1]);
-			cell->setPort(ID::Y, bit);
+			Cell *new_cell = module->addCell(NEW_ID2_SUFFIX("muxcover"), ID($bmux));
+			new_cell->setPort(ID::A, mux.inputs);
+			new_cell->setPort(ID::S, mux.selects);
+			new_cell->setPort(ID::Y, bit);
+			new_cell->fixup_parameters();
+			new_cell->set_src_attribute(new_cell->get_src_attribute());
 			return;
 		}
 
 		if (GetSize(mux.inputs) == 8) {
 			count_muxes_by_type[2]++;
-			Cell *cell = module->addCell(NEW_ID, ID($_MUX8_));
-			cell->setPort(ID::A, mux.inputs[0]);
-			cell->setPort(ID::B, mux.inputs[1]);
-			cell->setPort(ID::C, mux.inputs[2]);
-			cell->setPort(ID::D, mux.inputs[3]);
-			cell->setPort(ID::E, mux.inputs[4]);
-			cell->setPort(ID::F, mux.inputs[5]);
-			cell->setPort(ID::G, mux.inputs[6]);
-			cell->setPort(ID::H, mux.inputs[7]);
-			cell->setPort(ID::S, mux.selects[0]);
-			cell->setPort(ID::T, mux.selects[1]);
-			cell->setPort(ID::U, mux.selects[2]);
-			cell->setPort(ID::Y, bit);
+			Cell *new_cell = module->addCell(NEW_ID2_SUFFIX("muxcover"), ID($bmux));
+			new_cell->setPort(ID::A, mux.inputs);
+			new_cell->setPort(ID::S, mux.selects);
+			new_cell->setPort(ID::Y, bit);
+			new_cell->fixup_parameters();
+			new_cell->set_src_attribute(new_cell->get_src_attribute());
 			return;
 		}
 
 		if (GetSize(mux.inputs) == 16) {
 			count_muxes_by_type[3]++;
-			Cell *cell = module->addCell(NEW_ID, ID($_MUX16_));
-			cell->setPort(ID::A, mux.inputs[0]);
-			cell->setPort(ID::B, mux.inputs[1]);
-			cell->setPort(ID::C, mux.inputs[2]);
-			cell->setPort(ID::D, mux.inputs[3]);
-			cell->setPort(ID::E, mux.inputs[4]);
-			cell->setPort(ID::F, mux.inputs[5]);
-			cell->setPort(ID::G, mux.inputs[6]);
-			cell->setPort(ID::H, mux.inputs[7]);
-			cell->setPort(ID::I, mux.inputs[8]);
-			cell->setPort(ID::J, mux.inputs[9]);
-			cell->setPort(ID::K, mux.inputs[10]);
-			cell->setPort(ID::L, mux.inputs[11]);
-			cell->setPort(ID::M, mux.inputs[12]);
-			cell->setPort(ID::N, mux.inputs[13]);
-			cell->setPort(ID::O, mux.inputs[14]);
-			cell->setPort(ID::P, mux.inputs[15]);
-			cell->setPort(ID::S, mux.selects[0]);
-			cell->setPort(ID::T, mux.selects[1]);
-			cell->setPort(ID::U, mux.selects[2]);
-			cell->setPort(ID::V, mux.selects[3]);
-			cell->setPort(ID::Y, bit);
+			Cell *new_cell = module->addCell(NEW_ID2_SUFFIX("muxcover"), ID($bmux));
+			new_cell->setPort(ID::A, mux.inputs);
+			new_cell->setPort(ID::S, mux.selects);
+			new_cell->setPort(ID::Y, bit);
+			new_cell->fixup_parameters();
+			new_cell->set_src_attribute(new_cell->get_src_attribute());
 			return;
 		}