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	Merge pull request #4926 from JasonBrave/filelist
Verilog file list suport
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						commit
						6884c98e08
					
				
					 3 changed files with 96 additions and 3 deletions
				
			
		
							
								
								
									
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			@ -7,6 +7,7 @@
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*.gcno
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*~
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__pycache__
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/.cache
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/.cproject
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/.project
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/.settings
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			@ -15,6 +16,7 @@ __pycache__
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/qtcreator.config
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/qtcreator.creator
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/qtcreator.creator.user
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/compile_commands.json
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/coverage.info
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/coverage_html
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/Makefile.conf
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			@ -4298,7 +4298,7 @@ struct ReadPass : public Pass {
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		log("\n");
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		log("    read {-f|-F} <command-file>\n");
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		log("\n");
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		log("Load and execute the specified command file. (Requires Verific.)\n");
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		log("Load and execute the specified command file.\n");
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		log("Check verific command for more information about supported commands in file.\n");
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		log("\n");
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		log("\n");
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			@ -4412,10 +4412,14 @@ struct ReadPass : public Pass {
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		if (args[1] == "-f" || args[1] == "-F") {
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			if (use_verific) {
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				args[0] = "verific";
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				Pass::call(design, args);
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			} else {
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				cmd_error(args, 1, "This version of Yosys is built without Verific support.\n");
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#if !defined(__wasm)
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				args[0] = "read_verilog_file_list";
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#else
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				cmd_error(args, 1, "Command files are not supported on this platform.\n");
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#endif
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			}
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			Pass::call(design, args);
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			return;
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		}
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			@ -26,6 +26,10 @@
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 *
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 */
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#if !defined(__wasm)
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#include <filesystem>
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#endif
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#include "verilog_frontend.h"
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#include "preproc.h"
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#include "kernel/yosys.h"
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			@ -672,6 +676,89 @@ struct VerilogDefines : public Pass {
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	}
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} VerilogDefines;
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#if !defined(__wasm)
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static void parse_file_list(const std::string &file_list_path, RTLIL::Design *design, bool relative_to_file_list_path)
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{
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	std::ifstream flist(file_list_path);
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	if (!flist.is_open()) {
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		log_error("Verilog file list file does not exist");
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		exit(1);
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	}
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	std::filesystem::path file_list_parent_dir = std::filesystem::path(file_list_path).parent_path();
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	std::string v_file_name;
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	while (std::getline(flist, v_file_name)) {
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		if (v_file_name.empty()) {
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			continue;
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		}
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		std::filesystem::path verilog_file_path;
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		if (relative_to_file_list_path) {
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			verilog_file_path = file_list_parent_dir / v_file_name;
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		} else {
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			verilog_file_path = std::filesystem::current_path() / v_file_name;
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		}
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		bool is_sv = (verilog_file_path.extension() == ".sv");
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		std::vector<std::string> read_verilog_cmd = {"read_verilog", "-defer"};
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		if (is_sv) {
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			read_verilog_cmd.push_back("-sv");
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		}
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		read_verilog_cmd.push_back(verilog_file_path.string());
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		Pass::call(design, read_verilog_cmd);
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	}
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	flist.close();
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}
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struct VerilogFileList : public Pass {
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	VerilogFileList() : Pass("read_verilog_file_list", "Parse a Verilog file list") {}
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	void help() override
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	{
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		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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		log("\n");
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		log("    read_verilog_file_list [options]\n");
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		log("\n");
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		log("Parse a Verilog file list, and pass the list of Verilog files to read_verilog\n");
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		log("command\n");
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		log("\n");
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		log("    -F file_list_path\n");
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		log("        File list file contains list of Verilog files to be parsed, any path is\n");
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		log("        treated relative to the file list file\n");
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		log("\n");
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		log("    -f file_list_path\n");
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		log("        File list file contains list of Verilog files to be parsed, any path is\n");
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		log("        treated relative to current working directroy\n");
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		log("\n");
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	}
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	void execute(std::vector<std::string> args, RTLIL::Design *design) override
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	{
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		size_t argidx;
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		for (argidx = 1; argidx < args.size(); argidx++) {
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			std::string arg = args[argidx];
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			if (arg == "-F" && argidx + 1 < args.size()) {
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				std::string file_list_path = args[++argidx];
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				parse_file_list(file_list_path, design, true);
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				continue;
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			}
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			if (arg == "-f" && argidx + 1 < args.size()) {
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				std::string file_list_path = args[++argidx];
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				parse_file_list(file_list_path, design, false);
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				continue;
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			}
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			break;
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		}
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		extra_args(args, argidx, design);
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	}
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} VerilogFilelist;
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#endif
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YOSYS_NAMESPACE_END
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// the yyerror function used by bison to report parser errors
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