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Merge branch 'main' into negopt-pass-pr

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This commit is contained in:
Akash Levy 2026-02-04 00:15:53 -08:00
commit 715e062bcd
8 changed files with 37 additions and 16 deletions
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2
Makefile
View file

@ -177,7 +177,7 @@ ifeq ($(OS), Haiku)
CXXFLAGS += -D_DEFAULT_SOURCE CXXFLAGS += -D_DEFAULT_SOURCE
endif endif
YOSYS_VER := 0.61+112 YOSYS_VER := 0.61+129
YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)

2
abc

@ -1 +1 @@
Subproject commit 79010216cb87427dd7a0c8d38f156494221be006 Subproject commit 734f64d5b907158dc4337ee82b3b74566d74ba08

8
frontends/verific/verific.cc
View file

@ -3143,9 +3143,6 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
if (verific_opt) { if (verific_opt) {
log(" Optimizing netlist for %s.\n", it->first.c_str()); log(" Optimizing netlist for %s.\n", it->first.c_str());
// log(" Inferring clock enable muxes for %s.\n", it->first.c_str());
// nl->InferClockEnableMux();
log(" Running post-elaboration for %s.\n", it->first.c_str()); log(" Running post-elaboration for %s.\n", it->first.c_str());
nl->PostElaborationProcess(); nl->PostElaborationProcess();
@ -3864,14 +3861,17 @@ struct VerificPass : public Pass {
{ {
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
unsigned verilog_mode = veri_file::UNDEFINED; unsigned verilog_mode = veri_file::UNDEFINED;
#ifdef VERIFIC_VHDL_SUPPORT
unsigned vhdl_mode = vhdl_file::UNDEFINED; unsigned vhdl_mode = vhdl_file::UNDEFINED;
bool is_formal = false;
#endif #endif
bool is_formal = false;
#else
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
unsigned verilog_mode = veri_file::SYSTEM_VERILOG; unsigned verilog_mode = veri_file::SYSTEM_VERILOG;
#endif #endif
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT
unsigned vhdl_mode = vhdl_file::UNDEFINED; unsigned vhdl_mode = vhdl_file::UNDEFINED;
#endif
#endif #endif
const char* filename = nullptr; const char* filename = nullptr;

6
kernel/rtlil.cc
View file

@ -1612,12 +1612,6 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartial
return result; return result;
} }
void RTLIL::Design::run_pass(std::string command) {
log("\n-- Running command `%s' --\n", command.c_str());
Pass::call(this, command);
log_flush();
}
RTLIL::Module::Module() RTLIL::Module::Module()
{ {
static unsigned int hashidx_count = 123456789; static unsigned int hashidx_count = 123456789;

3
kernel/rtlil.h
View file

@ -2039,9 +2039,6 @@ struct RTLIL::Design
// partially selected or boxed modules have been ignored // partially selected or boxed modules have been ignored
std::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); } std::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }
// SILIMATE ADDED TO IMPROVE PYOSYS API
void run_pass(std::string command);
static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void); static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
std::string to_rtlil_str(bool only_selected = true) const; std::string to_rtlil_str(bool only_selected = true) const;

2
passes/techmap/abc.cc
View file

@ -2844,4 +2844,4 @@ struct AbcPass : public Pass {
} }
} AbcPass; } AbcPass;
PRIVATE_NAMESPACE_END PRIVATE_NAMESPACE_END

10
pyosys/generator.py
View file

@ -708,6 +708,16 @@ class PyosysWrapperGenerator(object):
self.process_class_members(metadata, metadata, cls, basename) self.process_class_members(metadata, metadata, cls, basename)
if basename == "Design":
print(
'\t\t\t.def("run_pass", [](Design &s, std::vector<std::string> cmd) { Pass::call(&s, cmd); })',
file=self.f,
)
print(
'\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(&s, cmd); })',
file=self.f,
)
if expr := metadata.string_expr: if expr := metadata.string_expr:
print( print(
f'\t\t.def("__str__", [](const {basename} &s) {{ return {expr}; }})', f'\t\t.def("__str__", [](const {basename} &s) {{ return {expr}; }})',

20
tests/pyosys/test_design_run_pass.py Normal file
View file

@ -0,0 +1,20 @@
from pathlib import Path
from pyosys import libyosys as ys
__file_dir__ = Path(__file__).absolute().parent
add_sub = __file_dir__.parent / "arch" / "common" / "add_sub.v"
base = ys.Design()
base.run_pass(["read_verilog", str(add_sub)])
base.run_pass("hierarchy -top top")
base.run_pass(["proc"])
base.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5")
postopt = ys.Design()
postopt.run_pass("design -load postopt")
postopt.run_pass(["cd", "top"])
postopt.run_pass("select -assert-min 25 t:LUT4")
postopt.run_pass("select -assert-max 26 t:LUT4")
postopt.run_pass(["select", "-assert-count", "10", "t:PFUMX"])
postopt.run_pass(["select", "-assert-count", "6", "t:L6MUX21"])
postopt.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D")