diff --git a/Makefile b/Makefile
index f17128daf..ae7de49e0 100644
--- a/Makefile
+++ b/Makefile
@@ -177,7 +177,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.61+112
+YOSYS_VER := 0.61+129
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)
diff --git a/abc b/abc
index 79010216c..734f64d5b 160000
--- a/abc
+++ b/abc
@@ -1 +1 @@
-Subproject commit 79010216cb87427dd7a0c8d38f156494221be006
+Subproject commit 734f64d5b907158dc4337ee82b3b74566d74ba08
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 28cc850a9..9a5ffc767 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -3143,9 +3143,6 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 		if (verific_opt) {
 			log("  Optimizing netlist for %s.\n", it->first.c_str());
 
-			// log("    Inferring clock enable muxes for %s.\n", it->first.c_str());
-			// nl->InferClockEnableMux();
-
 			log("    Running post-elaboration for %s.\n", it->first.c_str());
 			nl->PostElaborationProcess();
 
@@ -3864,14 +3861,17 @@ struct VerificPass : public Pass {
 		{
 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
 			unsigned verilog_mode = veri_file::UNDEFINED;
+#ifdef VERIFIC_VHDL_SUPPORT
 			unsigned vhdl_mode = vhdl_file::UNDEFINED;
-			bool is_formal = false;
 #endif
+			bool is_formal = false;
+#else
 #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 			unsigned verilog_mode = veri_file::SYSTEM_VERILOG;
 #endif
 #ifdef VERIFIC_VHDL_SUPPORT
 			unsigned vhdl_mode = vhdl_file::UNDEFINED;
+#endif
 #endif
 			const char* filename = nullptr;
 
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 43e4930d1..d27eabc25 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1612,12 +1612,6 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartial
 	return result;
 }
 
-void RTLIL::Design::run_pass(std::string command) {
-	log("\n-- Running command `%s' --\n", command.c_str());
-	Pass::call(this, command);
-	log_flush();
-}
-
 RTLIL::Module::Module()
 {
 	static unsigned int hashidx_count = 123456789;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 74675b079..ef9a077f3 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -2039,9 +2039,6 @@ struct RTLIL::Design
 	// partially selected or boxed modules have been ignored
 	std::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }
 
-	// SILIMATE ADDED TO IMPROVE PYOSYS API
-	void run_pass(std::string command);
-
 	static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
 
 	std::string to_rtlil_str(bool only_selected = true) const;
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 6f958292d..9b22c38f0 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -2844,4 +2844,4 @@ struct AbcPass : public Pass {
 	}
 } AbcPass;
 
-PRIVATE_NAMESPACE_END
+PRIVATE_NAMESPACE_END
\ No newline at end of file
diff --git a/pyosys/generator.py b/pyosys/generator.py
index 14c9421d9..d44ed9656 100644
--- a/pyosys/generator.py
+++ b/pyosys/generator.py
@@ -708,6 +708,16 @@ class PyosysWrapperGenerator(object):
 
         self.process_class_members(metadata, metadata, cls, basename)
 
+        if basename == "Design":
+            print(
+                '\t\t\t.def("run_pass", [](Design &s, std::vector<std::string> cmd) { Pass::call(&s, cmd); })',
+                file=self.f,
+            )
+            print(
+                '\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(&s, cmd); })',
+                file=self.f,
+            )
+
         if expr := metadata.string_expr:
             print(
                 f'\t\t.def("__str__", [](const {basename} &s) {{ return {expr}; }})',
diff --git a/tests/pyosys/test_design_run_pass.py b/tests/pyosys/test_design_run_pass.py
new file mode 100644
index 000000000..f0013577d
--- /dev/null
+++ b/tests/pyosys/test_design_run_pass.py
@@ -0,0 +1,20 @@
+from pathlib import Path
+from pyosys import libyosys as ys
+
+__file_dir__ = Path(__file__).absolute().parent
+add_sub = __file_dir__.parent / "arch" / "common" / "add_sub.v"
+
+base = ys.Design()
+base.run_pass(["read_verilog", str(add_sub)])
+base.run_pass("hierarchy -top top")
+base.run_pass(["proc"])
+base.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5")
+
+postopt = ys.Design()
+postopt.run_pass("design -load postopt")
+postopt.run_pass(["cd", "top"])
+postopt.run_pass("select -assert-min 25 t:LUT4")
+postopt.run_pass("select -assert-max 26 t:LUT4")
+postopt.run_pass(["select", "-assert-count", "10", "t:PFUMX"])
+postopt.run_pass(["select", "-assert-count", "6", "t:L6MUX21"])
+postopt.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D")