add Testcases

Fix existing testcases
Fix edgecase where modules where counted as cells.

passes/cmds/stat.cc

@@ -666,9 +666,10 @@ statdata_t hierarchy_builder(const RTLIL::Design *design, const RTLIL::Module *t
 					mod_data.submodule_area += mod_stat.at(cell->type).area;
 					mod_data.num_submodules++;
 					mod_data.unknown_cell_area.erase(cell->type);
-					mod_data.num_cells -= mod_data.num_cells_by_type.erase(cell->type);
+					mod_data.num_cells -= (mod_data.num_cells_by_type.count(cell->type) != 0)?  mod_data.num_cells_by_type.at(cell->type): 0;
-					mod_data.area_cells_by_type.erase(cell->type);
+					mod_data.num_cells_by_type.erase(cell->type);
-					mod_data.local_num_cells -= mod_data.local_num_cells_by_type.erase(cell->type);
+					mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type) != 0)? mod_data.local_num_cells_by_type.at(cell->type): 0;
+					mod_data.local_num_cells_by_type.erase(cell->type);
 					mod_data.local_area_cells_by_type.erase(cell->type);
 				} else {
 					// deal with blackbox cells
@@ -680,9 +681,10 @@ statdata_t hierarchy_builder(const RTLIL::Design *design, const RTLIL::Module *t
 						  double(design->module(cell->type)->attributes.at(ID::area).as_int());
 						mod_data.area += double(design->module(cell->type)->attributes.at(ID::area).as_int());
 						mod_data.unknown_cell_area.erase(cell->type);
-						mod_data.num_cells -= mod_data.num_cells_by_type.erase(cell->type);
+						mod_data.num_cells -= (mod_data.num_cells_by_type.count(cell->type) != 0)?  mod_data.num_cells_by_type.at(cell->type): 0;
-						mod_data.area_cells_by_type.erase(cell->type);
+						mod_data.num_cells_by_type.erase(cell->type);
-						mod_data.local_num_cells -= mod_data.local_num_cells_by_type.erase(cell->type);
+						mod_data.local_num_cells -= (mod_data.local_num_cells_by_type.count(cell->type) != 0)? mod_data.local_num_cells_by_type.at(cell->type): 0;
+						mod_data.local_num_cells_by_type.erase(cell->type);
 						mod_data.local_area_cells_by_type.erase(cell->type);
 					}
 				}
@@ -861,7 +863,7 @@ struct StatPass : public Pass {
 				mod_stat[top_mod->name].print_log_header(has_area, hierarchy_mode, true);
 				mod_stat[top_mod->name].print_log_line(log_id(top_mod->name), mod_stat[top_mod->name].local_num_cells,
 								       mod_stat[top_mod->name].local_area, mod_stat[top_mod->name].num_cells,
-								       mod_stat[top_mod->name].area, 0, has_area, hierarchy_mode);
+								       mod_stat[top_mod->name].area, 0, has_area, hierarchy_mode, true);
 			}
 
 			statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0, /*quiet=*/json_mode, has_area, hierarchy_mode);

tests/various/stat.ys

@@ -11,6 +11,8 @@ end
 EOT
 logger -expect log "Chip area for module '\\top': 9.072000" 1
 logger -expect-no-warnings
+logger -expect log "        1    9.072 cells" 1
+logger -expect log "        1    9.072   sg13g2_and2_1" 1
 stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz
 
 
@@ -69,6 +71,9 @@ module \child
 end
 EOT
 logger -expect log "Chip area for top module '\\top': 112.492800" 1
-logger -expect log "of which used for sequential elements: 94.348800" 1
+logger -expect log "of which used for sequential elements: 94.348800" 2
+logger -expect log "2   18.144 cells" 1 
+logger -expect log "4  112.493 cells" 1
+logger -expect log "2   94.349   sg13g2_dfrbp_1" 1
 logger -expect-no-warnings
 stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top

tests/various/stat_hierarchy.ys

@@ -0,0 +1,62 @@
+
+read_rtlil << EOT
+module \top
+  wire input 1 \A
+  wire output 2 \Y
+  wire output 3 \N
+
+  cell \sg13g2_and2_1 \sub1
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+
+  cell \child \sequential
+    connect \A \A
+    connect \B 1'0
+    connect \R 1'0
+    connect \Y \Y
+    connect \N \N
+  end
+
+  cell \child \sequential1
+    connect \A \A
+    connect \B 1'0
+    connect \R 1'0
+    connect \Y \Y
+    connect \N \N
+  end
+
+  cell \sg13g2_and2_1 \sub2
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+end
+
+module \child
+  wire input 1 \A
+  wire input 2 \B
+  wire input 3 \R
+
+  wire output 4 \Y
+  wire output 5 \N
+
+  cell \sg13g2_dfrbp_1 \sequential_ff
+    connect \CLK \A
+    connect \D \B
+    connect \Q \Y
+    connect \Q_N \N
+    connect \RESET_B \R
+  end
+
+end
+EOT
+logger -expect log "4  112.493        2   18.144 cells" 2 
+logger -expect log "2   18.144        2   18.144   sg13g2_and2_1" 2
+logger -expect log "2   94.349        -        -   sg13g2_dfrbp_1" 2
+logger -expect log "2   94.349        2        - submodules" 2
+logger -expect-no-warnings
+stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top -hierarchy
+
+