From d36a387aca39402b1da7ca9fb26c538f07d0a8b6 Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Thu, 7 Nov 2024 19:49:25 -0800 Subject: [PATCH 01/24] kernel/drivertools.h: avoid maybe-uninitialized compile warnings Initialize "unsigned int inner" in hash() functions Includes a log_assert() that might help catch corrupted data structures or future incomplete modification of DriveType definition --- kernel/drivertools.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/kernel/drivertools.h b/kernel/drivertools.h index 079701c35..21b5505d8 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -364,7 +364,7 @@ public: unsigned int hash() const { - unsigned int inner; + unsigned int inner = 0; switch (type_) { case DriveType::NONE: @@ -385,6 +385,9 @@ public: case DriveType::MULTIPLE: inner = multiple_.hash(); break; + default: + log_assert(0); + break; } return mkhash((unsigned int)type_, inner); } @@ -912,7 +915,7 @@ public: unsigned int hash() const { - unsigned int inner; + unsigned int inner = 0; switch (type_) { case DriveType::NONE: @@ -933,6 +936,9 @@ public: case DriveType::MULTIPLE: inner = multiple_.hash(); break; + default: + log_assert(0); + break; } return mkhash((unsigned int)type_, inner); } From df391f58164c8c13b87d9b3c54b194bb1c50170f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 8 Nov 2024 14:57:04 +0100 Subject: [PATCH 02/24] verific: fix blackbox regression and add test case --- frontends/verific/verific.cc | 1 + tests/verific/blackbox.ys | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 tests/verific/blackbox.ys diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 0cdf772a8..4233e73ba 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3428,6 +3428,7 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_preserve_assignments", 1); RuntimeFlags::SetVar("veri_preserve_comments", 1); RuntimeFlags::SetVar("veri_preserve_drivers", 1); + RuntimeFlags::SetVar("veri_create_empty_box", 1); // Workaround for VIPER #13851 RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); diff --git a/tests/verific/blackbox.ys b/tests/verific/blackbox.ys new file mode 100644 index 000000000..fbf689e3d --- /dev/null +++ b/tests/verific/blackbox.ys @@ -0,0 +1,24 @@ +verific -sv -lib < Date: Fri, 8 Nov 2024 10:30:11 -0800 Subject: [PATCH 03/24] drivertools.h: switch from log_assert(0) to log_abort() for new feature --- kernel/drivertools.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/drivertools.h b/kernel/drivertools.h index 21b5505d8..8929c3426 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -386,7 +386,7 @@ public: inner = multiple_.hash(); break; default: - log_assert(0); + log_abort(); break; } return mkhash((unsigned int)type_, inner); @@ -937,7 +937,7 @@ public: inner = multiple_.hash(); break; default: - log_assert(0); + log_abort(); break; } return mkhash((unsigned int)type_, inner); From 1476eaba0070cfb92b8721c101b5942828d2a7d6 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 12 Nov 2024 16:23:12 +1300 Subject: [PATCH 04/24] Docs: Add fallback for missing furo_ys This is mainly intended for (latex)pdf builds which do not use the furo-ys html theme, where the yosys script syntax highlighting can safely fallback to plaintext. This effectively makes `furo-ys` an optional dependency to simplify distro-package maintainability. See also #4725. --- docs/source/conf.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/docs/source/conf.py b/docs/source/conf.py index 0de8cd445..c625d2814 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -87,5 +87,9 @@ def setup(app: Sphinx) -> None: from util.RtlilLexer import RtlilLexer app.add_lexer("RTLIL", RtlilLexer) - from furo_ys.lexers.YoscryptLexer import YoscryptLexer - app.add_lexer("yoscrypt", YoscryptLexer) + try: + from furo_ys.lexers.YoscryptLexer import YoscryptLexer + app.add_lexer("yoscrypt", YoscryptLexer) + except ModuleNotFoundError: + from pygments.lexers.special import TextLexer + app.add_lexer("yoscrypt", TextLexer) From 96c526d1ba57a465f970347ad30109c7d4c6e823 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Wed, 13 Nov 2024 10:21:44 +0100 Subject: [PATCH 05/24] Print a note about finding attribute (* top *) in hierarchy --- passes/hierarchy/hierarchy.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a8d7d5a53..8372c0339 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -1003,8 +1003,10 @@ struct HierarchyPass : public Pass { if (top_mod == nullptr) for (auto mod : design->modules()) - if (mod->get_bool_attribute(ID::top)) + if (mod->get_bool_attribute(ID::top)) { + log("Attribute `top' found on module `%s'. Setting top module to %s.\n", log_id(mod), log_id(mod)); top_mod = mod; + } if (top_mod == nullptr) { From 44b68fb4987dd746d5dd3c7ab751fdfd7f7a464f Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 20 Nov 2024 12:18:17 +1300 Subject: [PATCH 06/24] Docs: Add check for envvar to disable todos --- docs/source/conf.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/source/conf.py b/docs/source/conf.py index c625d2814..1f8a886e6 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -56,6 +56,9 @@ if os.getenv("READTHEDOCS"): else: release = yosys_ver todo_include_todos = False +elif os.getenv("YOSYS_DOCS_RELEASE"): + release = yosys_ver + todo_include_todos = False else: release = yosys_ver todo_include_todos = True From e649c1a8e1eebb4acb34af55c7e1b2f4fdeadaf9 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 20 Nov 2024 12:31:12 +1300 Subject: [PATCH 07/24] Docs: Accept empty string for release envvar --- docs/source/conf.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/conf.py b/docs/source/conf.py index 1f8a886e6..b9a908167 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -56,7 +56,7 @@ if os.getenv("READTHEDOCS"): else: release = yosys_ver todo_include_todos = False -elif os.getenv("YOSYS_DOCS_RELEASE"): +elif os.getenv("YOSYS_DOCS_RELEASE") is not None: release = yosys_ver todo_include_todos = False else: From d6bd521487944ded68d8590295581f178d94437a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 21 Nov 2024 13:43:26 +0100 Subject: [PATCH 08/24] verific : VHDL assert DFF initial value set on Verific library patch side --- frontends/verific/verific.cc | 6 ------ 1 file changed, 6 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index a247bc2eb..bdd3eafa2 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2126,12 +2126,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma log(" assert condition %s.\n", log_signal(cond)); Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1); - // Initialize FF feeding condition to 1, in case it is not - // used by rest of design logic, to prevent failing on - // initial uninitialized state - if (cond.is_wire() && !cond.wire->name.isPublic()) - cond.wire->attributes[ID::init] = Const(1,1); - import_attributes(cell->attributes, inst); continue; } From 4a057b3c447668b3c8e18b1f304de22e06762cca Mon Sep 17 00:00:00 2001 From: George Rennie Date: Thu, 21 Nov 2024 20:51:05 +0100 Subject: [PATCH 09/24] read_rtlil: warn on assigns after switches in case rules --- frontends/rtlil/rtlil_frontend.cc | 5 +++++ frontends/rtlil/rtlil_frontend.h | 1 + frontends/rtlil/rtlil_parser.y | 10 ++++++++++ 3 files changed, 16 insertions(+) diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc index 170ed560f..2c1910d13 100644 --- a/frontends/rtlil/rtlil_frontend.cc +++ b/frontends/rtlil/rtlil_frontend.cc @@ -31,6 +31,11 @@ void rtlil_frontend_yyerror(char const *s) YOSYS_NAMESPACE_PREFIX log_error("Parser error in line %d: %s\n", rtlil_frontend_yyget_lineno(), s); } +void rtlil_frontend_yywarning(char const *s) +{ + YOSYS_NAMESPACE_PREFIX log_warning("In line %d: %s\n", rtlil_frontend_yyget_lineno(), s); +} + YOSYS_NAMESPACE_BEGIN struct RTLILFrontend : public Frontend { diff --git a/frontends/rtlil/rtlil_frontend.h b/frontends/rtlil/rtlil_frontend.h index 189260605..31cfb80b4 100644 --- a/frontends/rtlil/rtlil_frontend.h +++ b/frontends/rtlil/rtlil_frontend.h @@ -42,6 +42,7 @@ YOSYS_NAMESPACE_END extern int rtlil_frontend_yydebug; int rtlil_frontend_yylex(void); void rtlil_frontend_yyerror(char const *s); +void rtlil_frontend_yywarning(char const *s); void rtlil_frontend_yyrestart(FILE *f); int rtlil_frontend_yyparse(void); int rtlil_frontend_yylex_destroy(void); diff --git a/frontends/rtlil/rtlil_parser.y b/frontends/rtlil/rtlil_parser.y index deb37d9a6..fc7615364 100644 --- a/frontends/rtlil/rtlil_parser.y +++ b/frontends/rtlil/rtlil_parser.y @@ -344,6 +344,16 @@ assign_stmt: TOK_ASSIGN sigspec sigspec EOL { if (attrbuf.size() != 0) rtlil_frontend_yyerror("dangling attribute"); + + // See https://github.com/YosysHQ/yosys/pull/4765 for discussion on this + // warning + if (!switch_stack.back()->empty()) { + rtlil_frontend_yywarning( + "case rule assign statements after switch statements may cause unexpected behaviour. " + "The assign statement is reordered to come before all switch statements." + ); + } + case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3)); delete $2; delete $3; From 8148ebd1ad395ebd6949e36daac3f5f86a03c9d6 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Thu, 21 Nov 2024 20:51:34 +0100 Subject: [PATCH 10/24] docs: document that assigns must come before switches in case rules --- docs/source/appendix/rtlil_text.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/source/appendix/rtlil_text.rst b/docs/source/appendix/rtlil_text.rst index 2c7a82d19..b1bc9c582 100644 --- a/docs/source/appendix/rtlil_text.rst +++ b/docs/source/appendix/rtlil_text.rst @@ -242,7 +242,7 @@ Processes Declares a process, with zero or more attributes, with the given identifier in the enclosing module. The body of a process consists of zero or more -assignments, exactly one switch, and zero or more syncs. +assignments followed by zero or more switches and zero or more syncs. See :ref:`sec:rtlil_process` for an overview of processes. @@ -250,7 +250,7 @@ See :ref:`sec:rtlil_process` for an overview of processes. ::= * ::= process - ::= * ? * * + ::= * * * ::= assign ::= ::= @@ -262,8 +262,8 @@ Switches Switches test a signal for equality against a list of cases. Each case specifies a comma-separated list of signals to check against. If there are no signals in the list, then the case is the default case. The body of a case consists of zero -or more switches and assignments. Both switches and cases may have zero or more -attributes. +or more assignments followed by zero or more switches. Both switches and cases +may have zero or more attributes. .. code:: BNF @@ -272,7 +272,7 @@ attributes. ::= * ::= case ? ::= (, )* - ::= ( | )* + ::= * * ::= end Syncs From 6ff5823d6a63bdb093584446ff3983f3c2b38761 Mon Sep 17 00:00:00 2001 From: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 26 Nov 2024 09:59:52 +1300 Subject: [PATCH 11/24] test-compile: Use clang-18 and gcc-14 The 'newest' compilers are actually not all that new, they're just the default for the image. Instead provide explicit versions. --- .github/workflows/test-compile.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 089e65ca7..f916e9a4c 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -33,8 +33,8 @@ jobs: - 'clang-14' - 'gcc-10' # newest - - 'clang' - - 'gcc' + - 'clang-18' + - 'gcc-14' include: # macOS - os: macos-13 @@ -72,7 +72,7 @@ jobs: # maximum standard, only on newest compilers - name: Build C++20 - if: ${{ matrix.compiler == 'clang' || matrix.compiler == 'gcc'}} + if: ${{ matrix.compiler == 'clang-18' || matrix.compiler == 'gcc-14' }} shell: bash run: | make config-$CC_SHORT From 1e0e367aeda8760407bd8efd81e85580a074ae19 Mon Sep 17 00:00:00 2001 From: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 26 Nov 2024 10:18:09 +1300 Subject: [PATCH 12/24] test-compile: Drop back to gcc-13 --- .github/workflows/test-compile.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index f916e9a4c..74c3e2639 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -32,9 +32,9 @@ jobs: # oldest supported - 'clang-14' - 'gcc-10' - # newest + # newest, make sure to update maximum standard step to match - 'clang-18' - - 'gcc-14' + - 'gcc-13' include: # macOS - os: macos-13 @@ -72,7 +72,7 @@ jobs: # maximum standard, only on newest compilers - name: Build C++20 - if: ${{ matrix.compiler == 'clang-18' || matrix.compiler == 'gcc-14' }} + if: ${{ matrix.compiler == 'clang-18' || matrix.compiler == 'gcc-13' }} shell: bash run: | make config-$CC_SHORT From 98b4affc4a03d65e2fb3e0854f2e916e3f75e5d6 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 26 Nov 2024 01:25:27 +0000 Subject: [PATCH 13/24] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index f30286363..1a9e577df 100644 --- a/Makefile +++ b/Makefile @@ -155,7 +155,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.47+116 +YOSYS_VER := 0.47+121 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From f42816325217e16169abaf135e639e04490a55ad Mon Sep 17 00:00:00 2001 From: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 28 Nov 2024 11:19:16 +1300 Subject: [PATCH 14/24] Move get_blackbox_attribute method to Module instead of AttrObject --- kernel/rtlil.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0f3984ab8..f0ddb3927 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -814,6 +814,7 @@ struct RTLIL::AttrObject void set_bool_attribute(const RTLIL::IdString &id, bool value=true); bool get_bool_attribute(const RTLIL::IdString &id) const; + [[deprecated("Use Module::get_blackbox_attribute() instead.")]] bool get_blackbox_attribute(bool ignore_wb=false) const { return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox)); } @@ -1291,6 +1292,10 @@ public: virtual void optimize(); virtual void makeblackbox(); + bool get_blackbox_attribute(bool ignore_wb=false) const { + return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox)); + } + void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); void new_connections(const std::vector &new_conn); From 87742fa688cec95ceb089475726bc2404910ee36 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 28 Nov 2024 01:26:26 +0000 Subject: [PATCH 15/24] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 1a9e577df..36ec9bf21 100644 --- a/Makefile +++ b/Makefile @@ -155,7 +155,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.47+121 +YOSYS_VER := 0.47+135 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 6c78bd36372b0f38ea18cacf60996778448fe48e Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 28 Nov 2024 15:13:51 +0100 Subject: [PATCH 16/24] techmap: add a Han-Carlson option for `$lcu` mapping --- techlibs/common/Makefile.inc | 1 + techlibs/common/choices/han-carlson.v | 57 +++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 techlibs/common/choices/han-carlson.v diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index fa5c2a825..cb67d6329 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -36,3 +36,4 @@ $(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v)) $(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v)) $(eval $(call add_share_file,share,techlibs/common/cmp2softlogic.v)) $(eval $(call add_share_file,share/choices,techlibs/common/choices/kogge-stone.v)) +$(eval $(call add_share_file,share/choices,techlibs/common/choices/han-carlson.v)) diff --git a/techlibs/common/choices/han-carlson.v b/techlibs/common/choices/han-carlson.v new file mode 100644 index 000000000..4c93c6f7e --- /dev/null +++ b/techlibs/common/choices/han-carlson.v @@ -0,0 +1,57 @@ +(* techmap_celltype = "$lcu" *) +module _85_lcu_han_carlson (P, G, CI, CO); + parameter WIDTH = 2; + + (* force_downto *) + input [WIDTH-1:0] P, G; + input CI; + + (* force_downto *) + output [WIDTH-1:0] CO; + + integer i, j; + (* force_downto *) + reg [WIDTH-1:0] p, g; + + always @* begin + i = 0; + p = P; + g = G; + + // in almost all cases CI will be constant zero + g[0] = g[0] | (p[0] & CI); + if (i < $clog2(WIDTH)) begin + + // First layer: BK + for (j = WIDTH - 1; j >= 0; j = j - 1) begin + if (j % 2 == 1) begin + g[j] = g[j] | p[j] & g[j - 1]; + p[j] = p[j] & p[j - 1]; + end + end + + // Inner (log(WIDTH) - 1) layers: KS + for (i = 1; i < $clog2(WIDTH); i = i + 1) begin + for (j = WIDTH - 1; j >= 2**i; j = j - 1) begin + if (j % 2 == 1) begin + g[j] = g[j] | p[j] & g[j - 2**i]; + p[j] = p[j] & p[j - 2**i]; + end + end + end + + // Last layer: BK + if (i < ($clog2(WIDTH) + 1)) begin + for (j = WIDTH - 1; j >= 0; j = j - 1) begin + if ((j % 2 == 0) && (j > 0)) begin + g[j] = g[j] | p[j] & g[j - 1]; + p[j] = p[j] & p[j - 1]; + end + end + end + + end + end + + assign CO = g; +endmodule From 289673a807817692489243355588639bdaba46e9 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 28 Nov 2024 15:14:15 +0100 Subject: [PATCH 17/24] tests: add support for tcl tests --- tests/gen-tests-makefile.sh | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/tests/gen-tests-makefile.sh b/tests/gen-tests-makefile.sh index 2b26d8c98..b997fa12d 100755 --- a/tests/gen-tests-makefile.sh +++ b/tests/gen-tests-makefile.sh @@ -20,6 +20,13 @@ generate_ys_test() { generate_target "$ys_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${ys_file%.*}.log $yosys_args_ $ys_file" } +# $ generate_tcl_test tcl_file [yosys_args] +generate_tcl_test() { + tcl_file=$1 + yosys_args_=${2:-} + generate_target "$tcl_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${tcl_file%.*}.log $yosys_args_ $tcl_file" +} + # $ generate_bash_test bash_file generate_bash_test() { bash_file=$1 @@ -29,6 +36,7 @@ generate_bash_test() { # $ generate_tests [-y|--yosys-scripts] [-s|--prove-sv] [-b|--bash] [-a|--yosys-args yosys_args] generate_tests() { do_ys=false + do_tcl=false do_sv=false do_sh=false yosys_args="" @@ -40,6 +48,10 @@ generate_tests() { do_ys=true shift ;; + -t|--tcl-scripts) + do_tcl=true + shift + ;; -s|--prove-sv) do_sv=true shift @@ -59,7 +71,7 @@ generate_tests() { esac done - if [[ ! ( $do_ys = true || $do_sv = true || $do_sh = true ) ]]; then + if [[ ! ( $do_ys = true || $do_tcl = true || $do_sv = true || $do_sh = true ) ]]; then echo >&2 "Error: No file types selected" exit 1 fi @@ -72,6 +84,11 @@ generate_tests() { generate_ys_test "$x" "$yosys_args" done fi; + if [[ $do_tcl = true ]]; then + for x in *.tcl; do + generate_tcl_test "$x" "$yosys_args" + done + fi; if [[ $do_sv = true ]]; then for x in *.sv; do if [ ! -f "${x%.sv}.ys" ]; then From 1a562f9605aa689f634e3c8c5ed0b7ec2d82352c Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 28 Nov 2024 15:16:48 +0100 Subject: [PATCH 18/24] techmap: add TCL test for Han-Carlson adder --- tests/techmap/han-carlson.nomatch | 2 ++ tests/techmap/han-carlson.tcl | 14 ++++++++++++++ tests/techmap/lcu_refined.v | 20 ++++++++++++++++++++ tests/techmap/run-test.sh | 2 +- 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 tests/techmap/han-carlson.nomatch create mode 100644 tests/techmap/han-carlson.tcl create mode 100644 tests/techmap/lcu_refined.v diff --git a/tests/techmap/han-carlson.nomatch b/tests/techmap/han-carlson.nomatch new file mode 100644 index 000000000..142d509b3 --- /dev/null +++ b/tests/techmap/han-carlson.nomatch @@ -0,0 +1,2 @@ +i +j \ No newline at end of file diff --git a/tests/techmap/han-carlson.tcl b/tests/techmap/han-carlson.tcl new file mode 100644 index 000000000..114ebe4dc --- /dev/null +++ b/tests/techmap/han-carlson.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog +/choices/han-carlson.v +read_verilog lcu_refined.v +design -save init + +for {set i 1} {$i <= 16} {incr i} { + design -load init + chparam -set WIDTH $i + yosys proc + equiv_make -blacklist han-carlson.nomatch lcu _85_lcu_han_carlson equiv + equiv_simple equiv + equiv_status -assert equiv +} diff --git a/tests/techmap/lcu_refined.v b/tests/techmap/lcu_refined.v new file mode 100644 index 000000000..9187f68fe --- /dev/null +++ b/tests/techmap/lcu_refined.v @@ -0,0 +1,20 @@ +// Copied from techlibs/common/simlib.v +// with this condition removed: (^{P, G, CI} !== 1'bx) +module lcu (P, G, CI, CO); + +parameter WIDTH = 2; + +input [WIDTH-1:0] P; // Propagate +input [WIDTH-1:0] G; // Generate +input CI; // Carry-in + +output reg [WIDTH-1:0] CO; // Carry-out + +integer i; +always @* begin + CO[0] = G[0] || (P[0] && CI); + for (i = 1; i < WIDTH; i = i+1) + CO[i] = G[i] || (P[i] && CO[i-1]); +end + +endmodule diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh index 581847ab0..16741cace 100755 --- a/tests/techmap/run-test.sh +++ b/tests/techmap/run-test.sh @@ -1,4 +1,4 @@ #!/usr/bin/env bash set -eu source ../gen-tests-makefile.sh -run_tests --yosys-scripts --bash --yosys-args "-e 'select out of bounds'" +run_tests --yosys-scripts --tcl-scripts --bash --yosys-args "-e 'select out of bounds'" From 3f078d9afa464e3495fb657084beaf53d95a5297 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 28 Nov 2024 15:19:15 +0100 Subject: [PATCH 19/24] tests: rework Kogge-Stone test consistently with Han-Carlson --- tests/techmap/han-carlson.tcl | 2 +- tests/techmap/kogge-stone.tcl | 14 ++++++++++++++ tests/techmap/kogge-stone.ys | 1 - tests/techmap/{han-carlson.nomatch => ppa.nomatch} | 2 +- 4 files changed, 16 insertions(+), 3 deletions(-) create mode 100644 tests/techmap/kogge-stone.tcl delete mode 100644 tests/techmap/kogge-stone.ys rename tests/techmap/{han-carlson.nomatch => ppa.nomatch} (50%) diff --git a/tests/techmap/han-carlson.tcl b/tests/techmap/han-carlson.tcl index 114ebe4dc..0b5460be8 100644 --- a/tests/techmap/han-carlson.tcl +++ b/tests/techmap/han-carlson.tcl @@ -8,7 +8,7 @@ for {set i 1} {$i <= 16} {incr i} { design -load init chparam -set WIDTH $i yosys proc - equiv_make -blacklist han-carlson.nomatch lcu _85_lcu_han_carlson equiv + equiv_make -blacklist ppa.nomatch lcu _85_lcu_han_carlson equiv equiv_simple equiv equiv_status -assert equiv } diff --git a/tests/techmap/kogge-stone.tcl b/tests/techmap/kogge-stone.tcl new file mode 100644 index 000000000..e5f4e812c --- /dev/null +++ b/tests/techmap/kogge-stone.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog +/choices/kogge-stone.v +read_verilog lcu_refined.v +design -save init + +for {set i 1} {$i <= 16} {incr i} { + design -load init + chparam -set WIDTH $i + yosys proc + equiv_make -blacklist ppa.nomatch lcu _80_lcu_kogge_stone equiv + equiv_simple equiv + equiv_status -assert equiv +} diff --git a/tests/techmap/kogge-stone.ys b/tests/techmap/kogge-stone.ys deleted file mode 100644 index fc3637f10..000000000 --- a/tests/techmap/kogge-stone.ys +++ /dev/null @@ -1 +0,0 @@ -test_cell -s 1711533949 -n 10 -map +/techmap.v -map +/choices/kogge-stone.v $lcu diff --git a/tests/techmap/han-carlson.nomatch b/tests/techmap/ppa.nomatch similarity index 50% rename from tests/techmap/han-carlson.nomatch rename to tests/techmap/ppa.nomatch index 142d509b3..7388135e1 100644 --- a/tests/techmap/han-carlson.nomatch +++ b/tests/techmap/ppa.nomatch @@ -1,2 +1,2 @@ i -j \ No newline at end of file +j From 4bf3677640eac18b5afd2df63f11c56659194a9c Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 28 Nov 2024 23:54:00 +0100 Subject: [PATCH 20/24] techmap: set Han-Carlson adder priority consistent with Kogge-Stone --- techlibs/common/choices/han-carlson.v | 2 +- tests/techmap/han-carlson.tcl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/common/choices/han-carlson.v b/techlibs/common/choices/han-carlson.v index 4c93c6f7e..2ddcf75e9 100644 --- a/techlibs/common/choices/han-carlson.v +++ b/techlibs/common/choices/han-carlson.v @@ -1,5 +1,5 @@ (* techmap_celltype = "$lcu" *) -module _85_lcu_han_carlson (P, G, CI, CO); +module _80_lcu_han_carlson (P, G, CI, CO); parameter WIDTH = 2; (* force_downto *) diff --git a/tests/techmap/han-carlson.tcl b/tests/techmap/han-carlson.tcl index 0b5460be8..56a671ae6 100644 --- a/tests/techmap/han-carlson.tcl +++ b/tests/techmap/han-carlson.tcl @@ -8,7 +8,7 @@ for {set i 1} {$i <= 16} {incr i} { design -load init chparam -set WIDTH $i yosys proc - equiv_make -blacklist ppa.nomatch lcu _85_lcu_han_carlson equiv + equiv_make -blacklist ppa.nomatch lcu _80_lcu_han_carlson equiv equiv_simple equiv equiv_status -assert equiv } From a41ef0271ce922a9a945e5c97a65ca68b8a2df22 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 29 Nov 2024 00:03:49 +0100 Subject: [PATCH 21/24] techmap: remove ppa.nomatch by purging internal signals --- tests/techmap/han-carlson.tcl | 3 ++- tests/techmap/kogge-stone.tcl | 3 ++- tests/techmap/ppa.nomatch | 2 -- 3 files changed, 4 insertions(+), 4 deletions(-) delete mode 100644 tests/techmap/ppa.nomatch diff --git a/tests/techmap/han-carlson.tcl b/tests/techmap/han-carlson.tcl index 56a671ae6..3d32c7e02 100644 --- a/tests/techmap/han-carlson.tcl +++ b/tests/techmap/han-carlson.tcl @@ -8,7 +8,8 @@ for {set i 1} {$i <= 16} {incr i} { design -load init chparam -set WIDTH $i yosys proc - equiv_make -blacklist ppa.nomatch lcu _80_lcu_han_carlson equiv + opt_clean -purge + equiv_make lcu _80_lcu_han_carlson equiv equiv_simple equiv equiv_status -assert equiv } diff --git a/tests/techmap/kogge-stone.tcl b/tests/techmap/kogge-stone.tcl index e5f4e812c..243706284 100644 --- a/tests/techmap/kogge-stone.tcl +++ b/tests/techmap/kogge-stone.tcl @@ -8,7 +8,8 @@ for {set i 1} {$i <= 16} {incr i} { design -load init chparam -set WIDTH $i yosys proc - equiv_make -blacklist ppa.nomatch lcu _80_lcu_kogge_stone equiv + opt_clean -purge + equiv_make lcu _80_lcu_kogge_stone equiv equiv_simple equiv equiv_status -assert equiv } diff --git a/tests/techmap/ppa.nomatch b/tests/techmap/ppa.nomatch deleted file mode 100644 index 7388135e1..000000000 --- a/tests/techmap/ppa.nomatch +++ /dev/null @@ -1,2 +0,0 @@ -i -j From 91844968fd7565c4e31ce127b75730864e2331e2 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 29 Nov 2024 00:13:21 +0100 Subject: [PATCH 22/24] techmap: wrap builtin $lcu as golden module in PPA tests --- tests/techmap/han-carlson.tcl | 2 +- tests/techmap/kogge-stone.tcl | 2 +- tests/techmap/lcu_refined.v | 19 ++++++------------- 3 files changed, 8 insertions(+), 15 deletions(-) diff --git a/tests/techmap/han-carlson.tcl b/tests/techmap/han-carlson.tcl index 3d32c7e02..7029be57f 100644 --- a/tests/techmap/han-carlson.tcl +++ b/tests/techmap/han-carlson.tcl @@ -1,7 +1,7 @@ yosys -import read_verilog +/choices/han-carlson.v -read_verilog lcu_refined.v +read_verilog -icells lcu_refined.v design -save init for {set i 1} {$i <= 16} {incr i} { diff --git a/tests/techmap/kogge-stone.tcl b/tests/techmap/kogge-stone.tcl index 243706284..b6a4ef54e 100644 --- a/tests/techmap/kogge-stone.tcl +++ b/tests/techmap/kogge-stone.tcl @@ -1,7 +1,7 @@ yosys -import read_verilog +/choices/kogge-stone.v -read_verilog lcu_refined.v +read_verilog -icells lcu_refined.v design -save init for {set i 1} {$i <= 16} {incr i} { diff --git a/tests/techmap/lcu_refined.v b/tests/techmap/lcu_refined.v index 9187f68fe..e0747f3f2 100644 --- a/tests/techmap/lcu_refined.v +++ b/tests/techmap/lcu_refined.v @@ -1,20 +1,13 @@ -// Copied from techlibs/common/simlib.v -// with this condition removed: (^{P, G, CI} !== 1'bx) module lcu (P, G, CI, CO); + parameter WIDTH = 2; -parameter WIDTH = 2; + input [WIDTH-1:0] P, G; + input CI; -input [WIDTH-1:0] P; // Propagate -input [WIDTH-1:0] G; // Generate -input CI; // Carry-in + output [WIDTH-1:0] CO; -output reg [WIDTH-1:0] CO; // Carry-out + reg [WIDTH-1:0] p, g; -integer i; -always @* begin - CO[0] = G[0] || (P[0] && CI); - for (i = 1; i < WIDTH; i = i+1) - CO[i] = G[i] || (P[i] && CO[i-1]); -end + \$lcu #(.WIDTH(WIDTH)) impl (.P(P), .G(G), .CI(CI), .CO(CO)); endmodule From 3ebc714dbc6a3247edd08ed9828d3ea56c2d3641 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 29 Nov 2024 00:15:02 +0100 Subject: [PATCH 23/24] techmap: test consistently with other equiv_make tests --- tests/techmap/han-carlson.tcl | 2 +- tests/techmap/kogge-stone.tcl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/techmap/han-carlson.tcl b/tests/techmap/han-carlson.tcl index 7029be57f..0d9068b5e 100644 --- a/tests/techmap/han-carlson.tcl +++ b/tests/techmap/han-carlson.tcl @@ -8,7 +8,7 @@ for {set i 1} {$i <= 16} {incr i} { design -load init chparam -set WIDTH $i yosys proc - opt_clean -purge + opt_clean equiv_make lcu _80_lcu_han_carlson equiv equiv_simple equiv equiv_status -assert equiv diff --git a/tests/techmap/kogge-stone.tcl b/tests/techmap/kogge-stone.tcl index b6a4ef54e..1209b1338 100644 --- a/tests/techmap/kogge-stone.tcl +++ b/tests/techmap/kogge-stone.tcl @@ -8,7 +8,7 @@ for {set i 1} {$i <= 16} {incr i} { design -load init chparam -set WIDTH $i yosys proc - opt_clean -purge + opt_clean equiv_make lcu _80_lcu_kogge_stone equiv equiv_simple equiv equiv_status -assert equiv From f04b89972123325dc48704f30e4f118aa24fca05 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 30 Nov 2024 00:21:43 +0000 Subject: [PATCH 24/24] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 36ec9bf21..444b0c4cd 100644 --- a/Makefile +++ b/Makefile @@ -155,7 +155,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.47+135 +YOSYS_VER := 0.47+149 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo