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Generate TRELLIS_DPR16X4 for lutram

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Miodrag Milanovic 2023-03-31 15:46:35 +02:00 • committed by myrtle
parent 6e12da3956
commit 6e4c1675e7
3 changed files with 72 additions and 21 deletions
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44
techlibs/machxo2/cells_sim.v
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@ -200,6 +200,50 @@ module DCMA (
);
endmodule
(* abc9_box, lib_whitebox *)
module TRELLIS_DPR16X4 (
input [3:0] DI,
input [3:0] WAD,
input WRE,
input WCK,
input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000;
reg [3:0] mem[15:0];
integer i;
initial begin
for (i = 0; i < 16; i = i + 1)
mem[i] <= INITVAL[4*i +: 4];
end
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
reg muxwre;
always @(*)
case (WREMUX)
"1": muxwre = 1'b1;
"0": muxwre = 1'b0;
"INV": muxwre = ~WRE;
default: muxwre = WRE;
endcase
always @(posedge muxwck)
if (muxwre)
mem[WAD] <= DI;
assign DO = mem[RAD];
specify
// TODO
(RAD *> DO) = 0;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module DPR16X4C (
input [3:0] DI,