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Merge 5c628387fd
into 08b3a9fc7b
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commit
6d621d5ca5
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@ -1395,7 +1395,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
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if (child->type == AST_MODULE || child->type == AST_INTERFACE)
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{
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for (auto n : design->verilog_globals)
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child->children.push_back(n->clone());
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child->children.insert(child->children.begin(), n->clone());
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// append nodes from previous packages using package-qualified names
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for (auto &n : design->verilog_packages) {
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