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use NEW_ID_SUFFIX
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1 changed files with 4 additions and 4 deletions
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@ -63,23 +63,23 @@ struct BreakSopPass : public Pass {
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pool<SigBit> intermed_wires;
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for (int i = 0; i < sop_depth; i++) {
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// Wire for the output
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auto and_out = module->addWire(NEW_ID2_SUFFIX("andterm_out"));
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auto and_out = module->addWire(NEW_ID_SUFFIX("andterm_out"));
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intermed_wires.insert(and_out);
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// Signals for the inputs
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pool<SigBit> and_in;
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for (int j = 0; j < sop_width; j++)
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if (sop_table[2 * (i * sop_width + j) + 0])
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and_in.insert(module->Not(NEW_ID2_SUFFIX(stringf("sop_in_%d_comp", j)), sop_inputs[j], false, cell->get_src_attribute()));
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and_in.insert(module->Not(NEW_ID_SUFFIX(stringf("sop_in_%d_comp", j)), sop_inputs[j], false, cell->get_src_attribute()));
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else if (sop_table[2 * (i * sop_width + j) + 1])
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and_in.insert(sop_inputs[j]);
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// Construct the cell
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module->addReduceAnd(NEW_ID2_SUFFIX("andterm"), and_in, and_out, false, cell->get_src_attribute());
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module->addReduceAnd(NEW_ID_SUFFIX("andterm"), and_in, and_out, false, cell->get_src_attribute());
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}
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// Construct the $reduce_or cell
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module->addReduceOr(NEW_ID2_SUFFIX("orterm"), intermed_wires, sop_output, false, cell->get_src_attribute());
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module->addReduceOr(NEW_ID_SUFFIX("orterm"), intermed_wires, sop_output, false, cell->get_src_attribute());
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// Mark the $sop cell for removal
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cells_to_remove.insert(cell);
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