diff --git a/passes/techmap/breaksop.cc b/passes/techmap/breaksop.cc
index 56769528d..9f039c5a0 100644
--- a/passes/techmap/breaksop.cc
+++ b/passes/techmap/breaksop.cc
@@ -63,23 +63,23 @@ struct BreakSopPass : public Pass {
 					pool<SigBit> intermed_wires;
 					for (int i = 0; i < sop_depth; i++) {
 						// Wire for the output
-						auto and_out = module->addWire(NEW_ID2_SUFFIX("andterm_out"));
+						auto and_out = module->addWire(NEW_ID_SUFFIX("andterm_out"));
 						intermed_wires.insert(and_out);
 
 						// Signals for the inputs
 						pool<SigBit> and_in;
 						for (int j = 0; j < sop_width; j++)
 							if (sop_table[2 * (i * sop_width + j) + 0])
-								and_in.insert(module->Not(NEW_ID2_SUFFIX(stringf("sop_in_%d_comp", j)), sop_inputs[j], false, cell->get_src_attribute()));
+								and_in.insert(module->Not(NEW_ID_SUFFIX(stringf("sop_in_%d_comp", j)), sop_inputs[j], false, cell->get_src_attribute()));
 							else if (sop_table[2 * (i * sop_width + j) + 1])
 								and_in.insert(sop_inputs[j]);
 
 						// Construct the cell
-						module->addReduceAnd(NEW_ID2_SUFFIX("andterm"), and_in, and_out, false, cell->get_src_attribute());
+						module->addReduceAnd(NEW_ID_SUFFIX("andterm"), and_in, and_out, false, cell->get_src_attribute());
 					}
 
 					// Construct the $reduce_or cell
-					module->addReduceOr(NEW_ID2_SUFFIX("orterm"), intermed_wires, sop_output, false, cell->get_src_attribute());
+					module->addReduceOr(NEW_ID_SUFFIX("orterm"), intermed_wires, sop_output, false, cell->get_src_attribute());
 
 					// Mark the $sop cell for removal
 					cells_to_remove.insert(cell);