Add -nocells flag to equiv_make and equiv_opt

The -nocells flag skips cell equivalence checking and only checks wire
equivalence. This is useful when optimizations preserve functionality but
rename or restructure cells, avoiding false negatives in equivalence checking.

tests/various/equiv_nocells.ys

@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module gold(input a, input b, output y);
+    assign y = a & b;
+endmodule
+
+module gate(input a, input b, output y);
+    assign y = a & b;
+endmodule
+EOT
+
+equiv_make -nocells gold gate equiv
+equiv_simple equiv
+equiv_status -assert equiv