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The -nocells flag skips cell equivalence checking and only checks wire equivalence. This is useful when optimizations preserve functionality but rename or restructure cells, avoiding false negatives in equivalence checking.
13 lines
253 B
Text
13 lines
253 B
Text
read_verilog <<EOT
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module gold(input a, input b, output y);
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assign y = a & b;
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endmodule
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module gate(input a, input b, output y);
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assign y = a & b;
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endmodule
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EOT
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equiv_make -nocells gold gate equiv
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equiv_simple equiv
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equiv_status -assert equiv
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