URAM mapping : Add test for 2048 x 144b

techlibs/xilinx/urams.txt

@@ -54,7 +54,6 @@ ram huge $__XILINX_URAM_SP_ {
 		portoption "RST_MODE" "ASYNC" {
 			rdarst zero;
 		}
-		wrtrans all new;
 		wrbe_separate;
 	}
 }

tests/arch/xilinx/priority_memory.v

@@ -79,7 +79,6 @@ module sp_write_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a);
 		rdata_a <= 'h0;
 	end
 
-
 	always @(posedge clk) begin
 		// A port
 		if (wren_a)
@@ -111,7 +110,6 @@ module sp_read_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a);
 		rdata_a <= 'h0;
 	end
 
-
 	always @(posedge clk) begin
 		// A port
 		if (wren_a)
@@ -120,3 +118,31 @@ module sp_read_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a);
 			rdata_a <= mem[addr_a];
 	end
 endmodule
+
+module sp_read_or_write (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a);
+
+	parameter ABITS = 11;
+	parameter WIDTH = 144;
+
+	input clk;
+	input wren_a, rden_a;
+	input [ABITS-1:0] addr_a;
+	input [WIDTH-1:0] wdata_a;
+	output reg [WIDTH-1:0] rdata_a;
+
+	(* ram_style = "huge" *)
+	reg [WIDTH-1:0] mem [0:2**ABITS-1];
+
+	integer i;
+	initial begin
+		rdata_a <= 'h0;
+	end
+
+	always @(posedge clk) begin
+		if (wren_a)
+			mem[addr_a] <= wdata_a;
+		else if (rden_a)
+			rdata_a <= mem[addr_a];
+	end
+
+endmodule

tests/arch/xilinx/priority_memory.ys

@@ -58,3 +58,13 @@ select -assert-count 1 t:URAM288
 #  see above for details
 select -assert-count 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i
 select -assert-none 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i
+
+# sp read or write for size 2048 x 144b
+# the two URAM ports A and B are concatenated, with port A serving LSBs and port B serving MSBs
+design -reset
+read_verilog priority_memory.v
+synth_xilinx -family xcup -top sp_read_or_write -noiopad
+select -assert-count 1 t:URAM288
+# we expect no more than 1 LUT2 to control the hardware enable ports
+#  see above for details about this command
+select -assert-max 1 t:LUT* n:*blif* %d