From 6bf758733825e2cf09996ec7bd3ff7d4a5f2dfc8 Mon Sep 17 00:00:00 2001 From: Adrien Prost-Boucle Date: Sat, 10 May 2025 14:53:56 +0200 Subject: [PATCH] URAM mapping : Add test for 2048 x 144b --- techlibs/xilinx/urams.txt | 1 - tests/arch/xilinx/priority_memory.v | 40 +++++++++++++++++++++++----- tests/arch/xilinx/priority_memory.ys | 10 +++++++ 3 files changed, 43 insertions(+), 8 deletions(-) diff --git a/techlibs/xilinx/urams.txt b/techlibs/xilinx/urams.txt index 2f881e583..f3d9602a3 100644 --- a/techlibs/xilinx/urams.txt +++ b/techlibs/xilinx/urams.txt @@ -54,7 +54,6 @@ ram huge $__XILINX_URAM_SP_ { portoption "RST_MODE" "ASYNC" { rdarst zero; } - wrtrans all new; wrbe_separate; } } diff --git a/tests/arch/xilinx/priority_memory.v b/tests/arch/xilinx/priority_memory.v index fc943e209..8aaa2792c 100644 --- a/tests/arch/xilinx/priority_memory.v +++ b/tests/arch/xilinx/priority_memory.v @@ -2,7 +2,7 @@ module priority_memory ( clk, wren_a, rden_a, addr_a, wdata_a, rdata_a, wren_b, rden_b, addr_b, wdata_b, rdata_b ); - + parameter ABITS = 12; parameter WIDTH = 72; @@ -30,7 +30,7 @@ module priority_memory ( mem[addr_a] <= wdata_a; else if (rden_a) rdata_a <= mem[addr_a]; - + // B port if (wren_b) mem[addr_b] <= wdata_b; @@ -47,7 +47,7 @@ module priority_memory ( mem[addr_b] <= wdata_b; else if (rden_b) rdata_b <= mem[addr_b]; - + // B port if (wren_a) mem[addr_a] <= wdata_a; @@ -79,12 +79,11 @@ module sp_write_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a); rdata_a <= 'h0; end - always @(posedge clk) begin // A port if (wren_a) mem[addr_a] <= wdata_a; - if (rden_a) + if (rden_a) if (wren_a) rdata_a <= wdata_a; else @@ -111,12 +110,39 @@ module sp_read_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a); rdata_a <= 'h0; end - always @(posedge clk) begin // A port if (wren_a) mem[addr_a] <= wdata_a; - if (rden_a) + if (rden_a) rdata_a <= mem[addr_a]; end endmodule + +module sp_read_or_write (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a); + + parameter ABITS = 11; + parameter WIDTH = 144; + + input clk; + input wren_a, rden_a; + input [ABITS-1:0] addr_a; + input [WIDTH-1:0] wdata_a; + output reg [WIDTH-1:0] rdata_a; + + (* ram_style = "huge" *) + reg [WIDTH-1:0] mem [0:2**ABITS-1]; + + integer i; + initial begin + rdata_a <= 'h0; + end + + always @(posedge clk) begin + if (wren_a) + mem[addr_a] <= wdata_a; + else if (rden_a) + rdata_a <= mem[addr_a]; + end + +endmodule diff --git a/tests/arch/xilinx/priority_memory.ys b/tests/arch/xilinx/priority_memory.ys index d0b2a16ad..9f1d2fb78 100644 --- a/tests/arch/xilinx/priority_memory.ys +++ b/tests/arch/xilinx/priority_memory.ys @@ -58,3 +58,13 @@ select -assert-count 1 t:URAM288 # see above for details select -assert-count 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i select -assert-none 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i + +# sp read or write for size 2048 x 144b +# the two URAM ports A and B are concatenated, with port A serving LSBs and port B serving MSBs +design -reset +read_verilog priority_memory.v +synth_xilinx -family xcup -top sp_read_or_write -noiopad +select -assert-count 1 t:URAM288 +# we expect no more than 1 LUT2 to control the hardware enable ports +# see above for details about this command +select -assert-max 1 t:LUT* n:*blif* %d