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URAM mapping : Add test for 2048 x 144b

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This commit is contained in:
Adrien Prost-Boucle 2025-05-10 14:53:56 +02:00
parent c7de531231
commit 6bf7587338
3 changed files with 43 additions and 8 deletions
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1
techlibs/xilinx/urams.txt
View file

@ -54,7 +54,6 @@ ram huge $__XILINX_URAM_SP_ {
portoption "RST_MODE" "ASYNC" { portoption "RST_MODE" "ASYNC" {
rdarst zero; rdarst zero;
} }
wrtrans all new;
wrbe_separate; wrbe_separate;
} }
} }

40
tests/arch/xilinx/priority_memory.v
View file

@ -2,7 +2,7 @@ module priority_memory (
clk, wren_a, rden_a, addr_a, wdata_a, rdata_a, clk, wren_a, rden_a, addr_a, wdata_a, rdata_a,
wren_b, rden_b, addr_b, wdata_b, rdata_b wren_b, rden_b, addr_b, wdata_b, rdata_b
); );
parameter ABITS = 12; parameter ABITS = 12;
parameter WIDTH = 72; parameter WIDTH = 72;
@ -30,7 +30,7 @@ module priority_memory (
mem[addr_a] <= wdata_a; mem[addr_a] <= wdata_a;
else if (rden_a) else if (rden_a)
rdata_a <= mem[addr_a]; rdata_a <= mem[addr_a];
// B port // B port
if (wren_b) if (wren_b)
mem[addr_b] <= wdata_b; mem[addr_b] <= wdata_b;
@ -47,7 +47,7 @@ module priority_memory (
mem[addr_b] <= wdata_b; mem[addr_b] <= wdata_b;
else if (rden_b) else if (rden_b)
rdata_b <= mem[addr_b]; rdata_b <= mem[addr_b];
// B port // B port
if (wren_a) if (wren_a)
mem[addr_a] <= wdata_a; mem[addr_a] <= wdata_a;
@ -79,12 +79,11 @@ module sp_write_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a);
rdata_a <= 'h0; rdata_a <= 'h0;
end end
always @(posedge clk) begin always @(posedge clk) begin
// A port // A port
if (wren_a) if (wren_a)
mem[addr_a] <= wdata_a; mem[addr_a] <= wdata_a;
if (rden_a) if (rden_a)
if (wren_a) if (wren_a)
rdata_a <= wdata_a; rdata_a <= wdata_a;
else else
@ -111,12 +110,39 @@ module sp_read_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a);
rdata_a <= 'h0; rdata_a <= 'h0;
end end
always @(posedge clk) begin always @(posedge clk) begin
// A port // A port
if (wren_a) if (wren_a)
mem[addr_a] <= wdata_a; mem[addr_a] <= wdata_a;
if (rden_a) if (rden_a)
rdata_a <= mem[addr_a]; rdata_a <= mem[addr_a];
end end
endmodule endmodule
module sp_read_or_write (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a);
parameter ABITS = 11;
parameter WIDTH = 144;
input clk;
input wren_a, rden_a;
input [ABITS-1:0] addr_a;
input [WIDTH-1:0] wdata_a;
output reg [WIDTH-1:0] rdata_a;
(* ram_style = "huge" *)
reg [WIDTH-1:0] mem [0:2**ABITS-1];
integer i;
initial begin
rdata_a <= 'h0;
end
always @(posedge clk) begin
if (wren_a)
mem[addr_a] <= wdata_a;
else if (rden_a)
rdata_a <= mem[addr_a];
end
endmodule

10
tests/arch/xilinx/priority_memory.ys
View file

@ -58,3 +58,13 @@ select -assert-count 1 t:URAM288
# see above for details # see above for details
select -assert-count 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i select -assert-count 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i
select -assert-none 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i select -assert-none 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i
# sp read or write for size 2048 x 144b
# the two URAM ports A and B are concatenated, with port A serving LSBs and port B serving MSBs
design -reset
read_verilog priority_memory.v
synth_xilinx -family xcup -top sp_read_or_write -noiopad
select -assert-count 1 t:URAM288
# we expect no more than 1 LUT2 to control the hardware enable ports
# see above for details about this command
select -assert-max 1 t:LUT* n:*blif* %d