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Move code in abc_module() that modifies the design into a new function extract()

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Splits up the big `abc_module()` function and isolates the code that modifies the design
after running ABC.
This commit is contained in:
Robert O'Callahan 2025-07-15 03:54:41 +00:00
parent 4e5e1a0388
commit 2a9d37fb12
1 changed files with 255 additions and 236 deletions
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491
passes/techmap/abc.cc
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@ -148,6 +148,7 @@ struct AbcModuleState {
dict<RTLIL::SigBit, int> signal_map;
FfInitVals initvals;
bool had_init = false;
bool did_run_abc = false;
bool clk_polarity = false;
bool en_polarity = false;
@ -158,6 +159,8 @@ struct AbcModuleState {
int undef_bits_lost = 0;
std::string tempdir_name;
AbcModuleState(const AbcConfig &config) : config(config) {}
int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1);
@ -168,6 +171,8 @@ struct AbcModuleState {
void handle_loops();
void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, const std::vector<RTLIL::Cell*> &cells,
bool dff_mode, std::string clk_str);
void extract(RTLIL::Design *design);
void finish();
};
int AbcModuleState::map_signal(RTLIL::SigBit bit, gate_type_t gate_type, int in1, int in2, int in3, int in4)
@ -823,7 +828,6 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_mo
if (dff_mode && clk_sig.empty())
log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
std::string tempdir_name;
if (config.cleanup)
tempdir_name = get_base_tmpdir() + "/";
else
@ -1193,194 +1197,155 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_mo
filt.next_line(line + "\n");
temp_stdouterr_r.close();
#endif
if (ret != 0)
if (ret != 0) {
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
buffer = stringf("%s/%s", tempdir_name.c_str(), "output.blif");
std::ifstream ifs;
ifs.open(buffer);
if (ifs.fail())
log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
bool builtin_lib = config.liberty_files.empty() && config.genlib_files.empty();
RTLIL::Design *mapped_design = new RTLIL::Design;
parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, config.sop_mode);
ifs.close();
log_header(design, "Re-integrating ABC results.\n");
RTLIL::Module *mapped_mod = mapped_design->module(ID(netlist));
if (mapped_mod == nullptr)
log_error("ABC output file does not contain a module `netlist'.\n");
for (auto w : mapped_mod->wires()) {
RTLIL::Wire *orig_wire = nullptr;
RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
if (orig_wire != nullptr && orig_wire->attributes.count(ID::src))
wire->attributes[ID::src] = orig_wire->attributes[ID::src];
if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx;
design->select(module, wire);
return;
}
did_run_abc = true;
return;
}
log("Don't call ABC as there is nothing to map.\n");
}
SigMap mapped_sigmap(mapped_mod);
FfInitVals mapped_initvals(&mapped_sigmap, mapped_mod);
void AbcModuleState::extract(RTLIL::Design *design)
{
if (!did_run_abc) {
return;
}
dict<std::string, int> cell_stats;
for (auto c : mapped_mod->cells())
std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "output.blif");
std::ifstream ifs;
ifs.open(buffer);
if (ifs.fail())
log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
bool builtin_lib = config.liberty_files.empty() && config.genlib_files.empty();
RTLIL::Design *mapped_design = new RTLIL::Design;
parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, config.sop_mode);
ifs.close();
log_header(design, "Re-integrating ABC results.\n");
RTLIL::Module *mapped_mod = mapped_design->module(ID(netlist));
if (mapped_mod == nullptr)
log_error("ABC output file does not contain a module `netlist'.\n");
for (auto w : mapped_mod->wires()) {
RTLIL::Wire *orig_wire = nullptr;
RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
if (orig_wire != nullptr && orig_wire->attributes.count(ID::src))
wire->attributes[ID::src] = orig_wire->attributes[ID::src];
if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx;
design->select(module, wire);
}
SigMap mapped_sigmap(mapped_mod);
FfInitVals mapped_initvals(&mapped_sigmap, mapped_mod);
dict<std::string, int> cell_stats;
for (auto c : mapped_mod->cells())
{
if (builtin_lib)
{
if (builtin_lib)
{
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type.in(ID(ZERO), ID(ONE))) {
RTLIL::SigSig conn;
RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
conn.first = module->wire(name_y);
conn.second = RTLIL::SigSpec(c->type == ID(ZERO) ? 0 : 1, 1);
module->connect(conn);
continue;
}
if (c->type == ID(BUF)) {
RTLIL::SigSig conn;
RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
RTLIL::IdString name_a = remap_name(c->getPort(ID::A).as_wire()->name);
conn.first = module->wire(name_y);
conn.second = module->wire(name_a);
module->connect(conn);
continue;
}
if (c->type == ID(NOT)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(AND), ID(OR), ID(XOR), ID(NAND), ID(NOR), ID(XNOR), ID(ANDNOT), ID(ORNOT))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(MUX), ID(NMUX))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::S, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type == ID(MUX4)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type == ID(MUX8)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type == ID(MUX16)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K,
ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI3), ID(OAI3))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI4), ID(OAI4))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type == ID(DFF)) {
log_assert(clk_sig.size() == 1);
FfData ff(module, &initvals, remap_name(c->name));
ff.width = 1;
ff.is_fine = true;
ff.has_clk = true;
ff.pol_clk = clk_polarity;
ff.sig_clk = clk_sig;
if (en_sig.size() != 0) {
log_assert(en_sig.size() == 1);
ff.has_ce = true;
ff.pol_ce = en_polarity;
ff.sig_ce = en_sig;
}
RTLIL::Const init = mapped_initvals(c->getPort(ID::Q));
if (had_init)
ff.val_init = init;
else
ff.val_init = State::Sx;
if (arst_sig.size() != 0) {
log_assert(arst_sig.size() == 1);
ff.has_arst = true;
ff.pol_arst = arst_polarity;
ff.sig_arst = arst_sig;
ff.val_arst = init;
}
if (srst_sig.size() != 0) {
log_assert(srst_sig.size() == 1);
ff.has_srst = true;
ff.pol_srst = srst_polarity;
ff.sig_srst = srst_sig;
ff.val_srst = init;
}
ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name));
RTLIL::Cell *cell = ff.emit();
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
design->select(module, cell);
continue;
}
}
else
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type.in(ID(_const0_), ID(_const1_))) {
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type.in(ID(ZERO), ID(ONE))) {
RTLIL::SigSig conn;
conn.first = module->wire(remap_name(c->connections().begin()->second.as_wire()->name));
conn.second = RTLIL::SigSpec(c->type == ID(_const0_) ? 0 : 1, 1);
RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
conn.first = module->wire(name_y);
conn.second = RTLIL::SigSpec(c->type == ID(ZERO) ? 0 : 1, 1);
module->connect(conn);
continue;
}
if (c->type == ID(_dff_)) {
if (c->type == ID(BUF)) {
RTLIL::SigSig conn;
RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
RTLIL::IdString name_a = remap_name(c->getPort(ID::A).as_wire()->name);
conn.first = module->wire(name_y);
conn.second = module->wire(name_a);
module->connect(conn);
continue;
}
if (c->type == ID(NOT)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(AND), ID(OR), ID(XOR), ID(NAND), ID(NOR), ID(XNOR), ID(ANDNOT), ID(ORNOT))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(MUX), ID(NMUX))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::S, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type == ID(MUX4)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type == ID(MUX8)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type == ID(MUX16)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K,
ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI3), ID(OAI3))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI4), ID(OAI4))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
for (auto name : {ID::A, ID::B, ID::C, ID::D, ID::Y}) {
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
design->select(module, cell);
continue;
}
if (c->type == ID(DFF)) {
log_assert(clk_sig.size() == 1);
FfData ff(module, &initvals, remap_name(c->name));
ff.width = 1;
@ -1390,6 +1355,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_mo
ff.sig_clk = clk_sig;
if (en_sig.size() != 0) {
log_assert(en_sig.size() == 1);
ff.has_ce = true;
ff.pol_ce = en_polarity;
ff.sig_ce = en_sig;
}
@ -1400,12 +1366,14 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_mo
ff.val_init = State::Sx;
if (arst_sig.size() != 0) {
log_assert(arst_sig.size() == 1);
ff.has_arst = true;
ff.pol_arst = arst_polarity;
ff.sig_arst = arst_sig;
ff.val_arst = init;
}
if (srst_sig.size() != 0) {
log_assert(srst_sig.size() == 1);
ff.has_srst = true;
ff.pol_srst = srst_polarity;
ff.sig_srst = srst_sig;
ff.val_srst = init;
@ -1417,69 +1385,116 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_mo
design->select(module, cell);
continue;
}
}
else
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
SigSpec my_a = module->wire(remap_name(c->getPort(ID::A).as_wire()->name));
SigSpec my_y = module->wire(remap_name(c->getPort(ID::Y).as_wire()->name));
module->connect(my_y, my_a);
continue;
}
RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->parameters = c->parameters;
for (auto &conn : c->connections()) {
RTLIL::SigSpec newsig;
for (auto &c : conn.second.chunks()) {
if (c.width == 0)
continue;
log_assert(c.width == 1);
newsig.append(module->wire(remap_name(c.wire->name)));
}
cell->setPort(conn.first, newsig);
}
design->select(module, cell);
if (c->type.in(ID(_const0_), ID(_const1_))) {
RTLIL::SigSig conn;
conn.first = module->wire(remap_name(c->connections().begin()->second.as_wire()->name));
conn.second = RTLIL::SigSpec(c->type == ID(_const0_) ? 0 : 1, 1);
module->connect(conn);
continue;
}
for (auto conn : mapped_mod->connections()) {
if (!conn.first.is_fully_const())
conn.first = module->wire(remap_name(conn.first.as_wire()->name));
if (!conn.second.is_fully_const())
conn.second = module->wire(remap_name(conn.second.as_wire()->name));
if (c->type == ID(_dff_)) {
log_assert(clk_sig.size() == 1);
FfData ff(module, &initvals, remap_name(c->name));
ff.width = 1;
ff.is_fine = true;
ff.has_clk = true;
ff.pol_clk = clk_polarity;
ff.sig_clk = clk_sig;
if (en_sig.size() != 0) {
log_assert(en_sig.size() == 1);
ff.pol_ce = en_polarity;
ff.sig_ce = en_sig;
}
RTLIL::Const init = mapped_initvals(c->getPort(ID::Q));
if (had_init)
ff.val_init = init;
else
ff.val_init = State::Sx;
if (arst_sig.size() != 0) {
log_assert(arst_sig.size() == 1);
ff.pol_arst = arst_polarity;
ff.sig_arst = arst_sig;
ff.val_arst = init;
}
if (srst_sig.size() != 0) {
log_assert(srst_sig.size() == 1);
ff.pol_srst = srst_polarity;
ff.sig_srst = srst_sig;
ff.val_srst = init;
}
ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name));
RTLIL::Cell *cell = ff.emit();
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
design->select(module, cell);
continue;
}
if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
SigSpec my_a = module->wire(remap_name(c->getPort(ID::A).as_wire()->name));
SigSpec my_y = module->wire(remap_name(c->getPort(ID::Y).as_wire()->name));
module->connect(my_y, my_a);
continue;
}
RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->parameters = c->parameters;
for (auto &conn : c->connections()) {
RTLIL::SigSpec newsig;
for (auto &c : conn.second.chunks()) {
if (c.width == 0)
continue;
log_assert(c.width == 1);
newsig.append(module->wire(remap_name(c.wire->name)));
}
cell->setPort(conn.first, newsig);
}
design->select(module, cell);
}
for (auto conn : mapped_mod->connections()) {
if (!conn.first.is_fully_const())
conn.first = module->wire(remap_name(conn.first.as_wire()->name));
if (!conn.second.is_fully_const())
conn.second = module->wire(remap_name(conn.second.as_wire()->name));
module->connect(conn);
}
cell_stats.sort();
for (auto &it : cell_stats)
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
int in_wires = 0, out_wires = 0;
for (auto &si : signal_list)
if (si.is_port) {
char buffer[100];
snprintf(buffer, 100, "\\ys__n%d", si.id);
RTLIL::SigSig conn;
if (si.type != G(NONE)) {
conn.first = si.bit;
conn.second = module->wire(remap_name(buffer));
out_wires++;
} else {
conn.first = module->wire(remap_name(buffer));
conn.second = si.bit;
in_wires++;
}
module->connect(conn);
}
log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
log("ABC RESULTS: input signals: %8d\n", in_wires);
log("ABC RESULTS: output signals: %8d\n", out_wires);
cell_stats.sort();
for (auto &it : cell_stats)
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
int in_wires = 0, out_wires = 0;
for (auto &si : signal_list)
if (si.is_port) {
char buffer[100];
snprintf(buffer, 100, "\\ys__n%d", si.id);
RTLIL::SigSig conn;
if (si.type != G(NONE)) {
conn.first = si.bit;
conn.second = module->wire(remap_name(buffer));
out_wires++;
} else {
conn.first = module->wire(remap_name(buffer));
conn.second = si.bit;
in_wires++;
}
module->connect(conn);
}
log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
log("ABC RESULTS: input signals: %8d\n", in_wires);
log("ABC RESULTS: output signals: %8d\n", out_wires);
delete mapped_design;
}
else
{
log("Don't call ABC as there is nothing to map.\n");
}
delete mapped_design;
}
void AbcModuleState::finish()
{
if (config.cleanup)
{
log("Removing temp directory.\n");
@ -2072,6 +2087,8 @@ struct AbcPass : public Pass {
AbcModuleState state(config);
state.assign_map.set(mod);
state.abc_module(design, mod, mod->selected_cells(), dff_mode, clk_str);
state.extract(design);
state.finish();
continue;
}
@ -2239,6 +2256,8 @@ struct AbcPass : public Pass {
state.srst_polarity = std::get<6>(it.first);
state.srst_sig = assign_map(std::get<7>(it.first));
state.abc_module(design, mod, it.second, !state.clk_sig.empty(), "$");
state.extract(design);
state.finish();
}
}