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Add proper test for SV-style arrays

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-06-20 12:06:07 +02:00
parent 2428fb7dc2
commit 6a6dd5e057
3 changed files with 16 additions and 6 deletions
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4
tests/various/unpacked_arrays.sv
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module unpacked_arrays;
reg array_range [0:7];
reg array_size [8];
endmodule

2
tests/various/unpacked_arrays.ys
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read_verilog -sv unpacked_arrays.sv
stat