From 6a5fea1b2733957003ef24f38313fb1c28fbf6d4 Mon Sep 17 00:00:00 2001
From: Gus Smith <guscomps@gmail.com>
Date: Mon, 30 Mar 2026 08:59:28 -0700
Subject: [PATCH] Regression test for #5765

---
 tests/various/muxpack_wide_y.ys | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 tests/various/muxpack_wide_y.ys

diff --git a/tests/various/muxpack_wide_y.ys b/tests/various/muxpack_wide_y.ys
new file mode 100644
index 000000000..142119875
--- /dev/null
+++ b/tests/various/muxpack_wide_y.ys
@@ -0,0 +1,9 @@
+# Regression test for issue #5734: muxpack crash when $logic_not / $eq / $reduce_or
+# has Y port width > 1 (e.g. boolean result assigned to a wide wire).
+read_verilog <<EOT
+module top(input b, output [18:0] h);
+  assign h = ~|b;
+endmodule
+EOT
+proc
+muxpack