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Collect parameters in hierarchy -generate (and do nothing with them)

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This commit is contained in:
Clifford Wolf 2013-03-26 19:11:53 +01:00
parent 26f2439551
commit 6a231816fa
1 changed files with 8 additions and 1 deletions
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9
passes/hierarchy/hierarchy.cc
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@ -50,17 +50,21 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
for (auto &celltype : found_celltypes) for (auto &celltype : found_celltypes)
{ {
std::set<std::string> portnames; std::set<std::string> portnames;
std::set<std::string> parameters;
std::map<std::string, int> portwidths; std::map<std::string, int> portwidths;
log("Generate module for cell type %s:\n", celltype.c_str()); log("Generate module for cell type %s:\n", celltype.c_str());
for (auto i1 : design->modules) for (auto i1 : design->modules)
for (auto i2 : i1.second->cells) for (auto i2 : i1.second->cells)
if (i2.second->type == celltype) if (i2.second->type == celltype) {
for (auto &conn : i2.second->connections) { for (auto &conn : i2.second->connections) {
if (conn.first[0] != '$') if (conn.first[0] != '$')
portnames.insert(conn.first); portnames.insert(conn.first);
portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.width); portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.width);
} }
for (auto &para : i2.second->parameters)
parameters.insert(para.first);
}
for (auto &decl : portdecls) for (auto &decl : portdecls)
if (decl.index > 0) if (decl.index > 0)
@ -121,6 +125,9 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
mod->add(wire); mod->add(wire);
} }
for (auto &para : parameters)
log(" ignoring parameter %s.\n", RTLIL::id2cstr(para));
log(" module %s created.\n", RTLIL::id2cstr(mod->name)); log(" module %s created.\n", RTLIL::id2cstr(mod->name));
} }
} }