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Revert sim's cycle_width default back to 10, but keep -width option

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Jannis Harder 2025-10-20 14:40:05 +02:00
parent f11a61b32b
commit 6a0ee6e4fb
2 changed files with 2 additions and 2 deletions
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tests/sim/sim_cycles.ys
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@ -2,7 +2,7 @@ read_verilog dff.v
prep
# create fst with 20 clock cycles (41 samples, 202ns)
sim -clock clk -fst sim_cycles.fst -n 20
sim -clock clk -fst sim_cycles.fst -width 2 -n 20
logger -expect-no-warnings