From 6a0ee6e4fb740840326d163599b6cad38933d26e Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Mon, 20 Oct 2025 14:40:05 +0200
Subject: [PATCH] Revert sim's cycle_width default back to 10, but keep -width
 option

---
 passes/sat/sim.cc       | 2 +-
 tests/sim/sim_cycles.ys | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 8f0886a4e..a29651653 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -2692,7 +2692,7 @@ struct SimPass : public Pass {
 	{
 		SimWorker worker;
 		int numcycles = 20;
-		int cycle_width = 2;
+		int cycle_width = 10;
 		int append = 0;
 		bool start_set = false, stop_set = false, at_set = false;
 
diff --git a/tests/sim/sim_cycles.ys b/tests/sim/sim_cycles.ys
index 0a13d9301..732b1fb81 100644
--- a/tests/sim/sim_cycles.ys
+++ b/tests/sim/sim_cycles.ys
@@ -2,7 +2,7 @@ read_verilog dff.v
 prep
 
 # create fst with 20 clock cycles (41 samples, 202ns)
-sim -clock clk -fst sim_cycles.fst -n 20
+sim -clock clk -fst sim_cycles.fst -width 2 -n 20
 
 logger -expect-no-warnings