mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-24 00:14:36 +00:00
Code Activity

Revert sim's cycle_width default back to 10, but keep -width option

Browse source
This commit is contained in:
Jannis Harder 2025-10-20 14:40:05 +02:00
parent f11a61b32b
commit 6a0ee6e4fb
2 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/sim/sim_cycles.ys
View file

@ -2,7 +2,7 @@ read_verilog dff.v
prep
# create fst with 20 clock cycles (41 samples, 202ns)
sim -clock clk -fst sim_cycles.fst -n 20
sim -clock clk -fst sim_cycles.fst -width 2 -n 20
logger -expect-no-warnings