Merge branch 'YosysHQ:master' into main/issue2525

tests/arch/gowin/compare.v

@@ -0,0 +1,20 @@
+module top
+(
+    input [4:0] x,
+    input [4:0] y,
+
+    output lt,
+    output le,
+    output gt,
+    output ge,
+    output eq,
+    output ne
+);
+
+    assign lt = x < y;
+    assign le = x <= y;
+    assign gt = x > y;
+    assign ge = x >= y;
+    assign eq = x == y;
+    assign ne = x != y;
+endmodule

tests/arch/gowin/compare.ys

@@ -0,0 +1,9 @@
+read_verilog compare.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 5 t:ALU
+
+

tests/liberty/issue3498_bad.lib

@@ -0,0 +1,8 @@
+library(fake) { 
+  cell(bugbad) { 
+    bundle(X) { 
+      members(x1, x2);
+      power_down_function : !a+b ; 
+    }
+  }
+}