From 131b5577278e4aa77d31a978f06d5aab51d2d58c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 19 Dec 2022 08:54:47 +0100 Subject: [PATCH 01/17] Initial implementation of synthesizable assertions --- passes/sat/Makefile.inc | 1 + passes/sat/synthprop.cc | 230 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 231 insertions(+) create mode 100644 passes/sat/synthprop.cc diff --git a/passes/sat/Makefile.inc b/passes/sat/Makefile.inc index ebe3dc536..cc89cc0c8 100644 --- a/passes/sat/Makefile.inc +++ b/passes/sat/Makefile.inc @@ -19,3 +19,4 @@ OBJS += passes/sat/fminit.o ifeq ($(DISABLE_SPAWN),0) OBJS += passes/sat/qbfsat.o endif +OBJS += passes/sat/synthprop.o diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc new file mode 100644 index 000000000..5bc1520bc --- /dev/null +++ b/passes/sat/synthprop.cc @@ -0,0 +1,230 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2022 Miodrag Milanovic + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +struct TrackingItem +{ + pool assertion_cells; + std::vector names; +}; + +typedef dict TrackingData; + +struct SynthPropWorker +{ + // pointer to main design + RTLIL::Design *design; + + RTLIL::IdString top_name; + + RTLIL::Module *module; + + std::string map_file; + + bool or_outputs; + + IdString port_name; + + // basic contrcutor + SynthPropWorker(RTLIL::Design *design) : design(design), or_outputs(false), port_name(RTLIL::escape_id("assertions")) {} + + void tracing(RTLIL::Module *mod, int depth, TrackingData &tracing_data, std::string hier_path); + void run(); +}; + +void SynthPropWorker::tracing(RTLIL::Module *mod, int depth, TrackingData &tracing_data, std::string hier_path) +{ + log("%*sTracing in module %s..\n", 2*depth, "", log_id(mod)); + tracing_data[mod] = TrackingItem(); + int cnt = 0; + for (auto cell : mod->cells()) { + if (cell->type == ID($assert)) { + log("%*sFound assert %s..\n", 2*(depth+1), "", log_id(cell)); + tracing_data[mod].assertion_cells.emplace(cell); + if (!or_outputs) { + tracing_data[mod].names.push_back(hier_path + "." + log_id(cell)); + } + cnt++; + } + else if (RTLIL::Module *submod = design->module(cell->type)) { + tracing(submod, depth+1, tracing_data, hier_path + "." + log_id(cell)); + if (!or_outputs) { + for (size_t i = 0; i < tracing_data[submod].names.size(); i++) + tracing_data[mod].names.push_back(tracing_data[submod].names[i]); + } else { + cnt += tracing_data[submod].names.size(); + } + } + } + if (or_outputs && (cnt > 0)) { + tracing_data[mod].names.push_back("merged_asserts"); + } +} + +void SynthPropWorker::run() +{ + if (!module->get_bool_attribute(ID::top)) + log_error("Module is not TOP module\n"); + + TrackingData tracing_data; + tracing(module, 0, tracing_data, log_id(module->name)); + + for (auto &data : tracing_data) { + if (data.second.names.size() == 0) continue; + RTLIL::Wire *wire = data.first->addWire(port_name, data.second.names.size()); + wire->port_output = true; + data.first->fixup_ports(); + } + + for (auto &data : tracing_data) { + int num = 0; + RTLIL::Wire *port_wire = data.first->wire(port_name); + pool connected; + for (auto cell : data.second.assertion_cells) { + if (cell->type == ID($assert)) { + RTLIL::Wire *neg_wire = data.first->addWire(NEW_ID); + RTLIL::Wire *result_wire = data.first->addWire(NEW_ID); + data.first->addNot(NEW_ID, cell->getPort(ID::A), neg_wire); + data.first->addAnd(NEW_ID, cell->getPort(ID::EN), neg_wire, result_wire); + if (!or_outputs) { + data.first->connect(SigBit(port_wire,num), result_wire); + } else { + connected.emplace(result_wire); + } + num++; + } + } + + for (auto cell : data.first->cells()) { + if (RTLIL::Module *submod = design->module(cell->type)) { + if (tracing_data[submod].names.size() > 0) { + if (!or_outputs) { + cell->setPort(port_name, SigChunk(port_wire, num, tracing_data[submod].names.size())); + } else { + RTLIL::Wire *result_wire = data.first->addWire(NEW_ID); + cell->setPort(port_name, result_wire); + connected.emplace(result_wire); + } + num += tracing_data[submod].names.size(); + } + } + } + if (or_outputs && connected.size() > 0) { + RTLIL::Wire *prev_wire = nullptr; + for (auto wire : connected ) { + if (!prev_wire) { + prev_wire = wire; + } else { + RTLIL::Wire *result = data.first->addWire(NEW_ID); + data.first->addOr(NEW_ID, prev_wire, wire, result); + prev_wire = result; + } + } + data.first->connect(port_wire, prev_wire); + } + } + + if (!map_file.empty()) { + std::ofstream fout; + fout.open(map_file, std::ios::out | std::ios::trunc); + if (!fout.is_open()) + log_error("Could not open file \"%s\" with write access.\n", map_file.c_str()); + + for (auto name : tracing_data[module].names) { + fout << name << std::endl; + } + } +} + +struct SyntProperties : public Pass { + SyntProperties() : Pass("synthprop", "synthesize SVA properties") { } + + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synthprop [options]\n"); + log("\n"); + log("This creates synthesizable properties for selected module.\n"); + log("\n"); + log("\n"); + log(" -name \n"); + log("\n"); + log("Name output port for assertions (default: assertions).\n"); + log("\n"); + log("\n"); + log(" -map \n"); + log("\n"); + log("Write port mapping for synthesizable properties.\n"); + log("\n"); + log("\n"); + log(" -or_outputs\n"); + log("\n"); + log("Or all outputs together to create a single output that goes high when any\n"); + log("property is violated, instead of generating individual output bits.\n"); + log("\n"); + log("\n"); + log(" -latch \n"); + log("\n"); + log("Latch a high state on the generated outputs until an asynchronous top-level\n"); + log("reset input is activated.\n"); + log("\n"); + log("\n"); + } + + virtual void execute(std::vector args, RTLIL::Design* design) + { + log_header(design, "Executing SYNTHPROP pass.\n"); + SynthPropWorker worker(design); + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-name" && argidx+1 < args.size()) { + worker.port_name = RTLIL::escape_id(args[++argidx]); + continue; + } + if (args[argidx] == "-map" && argidx+1 < args.size()) { + worker.map_file = args[++argidx]; + continue; + } + if (args[argidx] == "-latch" && argidx+2 < args.size()) { + continue; + } + if (args[argidx] == "-or_outputs") { + worker.or_outputs = true; + continue; + } + break; + } + + if (args.size() != argidx) + cmd_error(args, argidx, "Extra argument."); + + auto *top = design->top_module(); + if (top == nullptr) + log_cmd_error("Can't find top module in current design!\n"); + + worker.module = top; + worker.run(); + } +} SyntProperties; + +YOSYS_NAMESPACE_END From 713b7d3e262c777be649707112b81512bff94b5a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 19 Dec 2022 11:40:50 +0100 Subject: [PATCH 02/17] added support for latched output reset --- passes/sat/synthprop.cc | 47 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index 5bc1520bc..5dd1fefdf 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -43,6 +43,10 @@ struct SynthPropWorker IdString port_name; + IdString reset_name; + + bool reset_pol; + // basic contrcutor SynthPropWorker(RTLIL::Design *design) : design(design), or_outputs(false), port_name(RTLIL::escape_id("assertions")) {} @@ -94,9 +98,14 @@ void SynthPropWorker::run() data.first->fixup_ports(); } + RTLIL::Wire *output = nullptr; for (auto &data : tracing_data) { int num = 0; RTLIL::Wire *port_wire = data.first->wire(port_name); + if (!reset_name.empty() && data.first == module) { + port_wire = data.first->addWire(NEW_ID, data.second.names.size()); + output = port_wire; + } pool connected; for (auto cell : data.second.assertion_cells) { if (cell->type == ID($assert)) { @@ -142,6 +151,17 @@ void SynthPropWorker::run() } } + // If no assertions found + if (tracing_data[module].names.size() == 0) return; + + if (!reset_name.empty()) { + int width = tracing_data[module].names.size(); + SigSpec reset = module->wire(reset_name); + reset.extend_u0(width, true); + + module->addDlatchsr(NEW_ID, State::S1, Const(State::S0,width), reset, output, module->wire(port_name), true, true, reset_pol); + } + if (!map_file.empty()) { std::ofstream fout; fout.open(map_file, std::ios::out | std::ios::trunc); @@ -166,7 +186,7 @@ struct SyntProperties : public Pass { log("This creates synthesizable properties for selected module.\n"); log("\n"); log("\n"); - log(" -name \n"); + log(" -name \n"); log("\n"); log("Name output port for assertions (default: assertions).\n"); log("\n"); @@ -182,10 +202,16 @@ struct SyntProperties : public Pass { log("property is violated, instead of generating individual output bits.\n"); log("\n"); log("\n"); - log(" -latch \n"); + log(" -reset \n"); log("\n"); - log("Latch a high state on the generated outputs until an asynchronous top-level\n"); - log("reset input is activated.\n"); + log("Name of top-level reset input. Latch a high state on the generated outputs\n"); + log("until an asynchronous top-level reset input is activated.\n"); + log("\n"); + log("\n"); + log(" -resetn \n"); + log("\n"); + log("Name of top-level reset input (inverse polarity). Latch a high state on the\n"); + log("generated outputs until an asynchronous top-level reset input is activated.\n"); log("\n"); log("\n"); } @@ -205,7 +231,14 @@ struct SyntProperties : public Pass { worker.map_file = args[++argidx]; continue; } - if (args[argidx] == "-latch" && argidx+2 < args.size()) { + if (args[argidx] == "-reset" && argidx+1 < args.size()) { + worker.reset_name = RTLIL::escape_id(args[++argidx]); + worker.reset_pol = true; + continue; + } + if (args[argidx] == "-resetn" && argidx+1 < args.size()) { + worker.reset_name = RTLIL::escape_id(args[++argidx]); + worker.reset_pol = false; continue; } if (args[argidx] == "-or_outputs") { @@ -222,6 +255,10 @@ struct SyntProperties : public Pass { if (top == nullptr) log_cmd_error("Can't find top module in current design!\n"); + auto *reset = top->wire(worker.reset_name); + if (!worker.reset_name.empty() && reset == nullptr) + log_cmd_error("Can't find reset line in current design!\n"); + worker.module = top; worker.run(); } From 550a5b7b6b903be2691eb2e188e715ca121db2fb Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 5 Jan 2023 16:04:07 +0100 Subject: [PATCH 03/17] Update license --- passes/sat/synthprop.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index 5dd1fefdf..25416b6c4 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -1,7 +1,9 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2022 Miodrag Milanovic + * Copyright (C) 2023 Miodrag Milanovic + * Copyright (C) 2023 + * National Technology & Engineering Solutions of Sandia, LLC (NTESS) * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above From ec47bf174549f4f2430c08e0d24bb9ba7bd5390d Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Fri, 21 Apr 2023 16:51:42 +0200 Subject: [PATCH 04/17] verific: Handle conditions when using sva_at_only in VerificClocking This handles conditions on clocked concurrent assertions in unclocked procedural contexts. --- frontends/verific/verific.cc | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 605dcdfb2..bc61c9c82 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2011,6 +2011,28 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a Instance *inst = net->Driver(); + // Detect condition expression in sva_at_only mode + if (sva_at_only) + do { + Instance *inst_mux = net->Driver(); + if (inst_mux->Type() != PRIM_MUX) + break; + + bool pwr1 = inst_mux->GetInput1()->IsPwr(); + bool pwr2 = inst_mux->GetInput2()->IsPwr(); + + if (!pwr1 && !pwr2) + break; + + Net *sva_net = pwr1 ? inst_mux->GetInput2() : inst_mux->GetInput1(); + if (!verific_is_sva_net(importer, sva_net)) + break; + + inst = sva_net->Driver(); + cond_net = inst_mux->GetControl(); + cond_pol = pwr1; + } while (0); + if (inst != nullptr && inst->Type() == PRIM_SVA_AT) { net = inst->GetInput1(); From 3cbca5064cfbb418ac69d703034f8bb780a9cc41 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Fri, 21 Apr 2023 17:19:42 +0200 Subject: [PATCH 05/17] verific: Handle non-seq properties with VerificClocking conditions --- frontends/verific/verificsva.cc | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 986a98643..222c7d2e9 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1598,12 +1598,17 @@ struct VerificSvaImporter if (inst == nullptr) { - log_assert(trig == State::S1); - - if (accept_p != nullptr) - *accept_p = importer->net_map_at(net); - if (reject_p != nullptr) - *reject_p = module->Not(NEW_ID, importer->net_map_at(net)); + if (trig != State::S1) { + if (accept_p != nullptr) + *accept_p = module->And(NEW_ID, trig, importer->net_map_at(net)); + if (reject_p != nullptr) + *reject_p = module->And(NEW_ID, trig, module->Not(NEW_ID, importer->net_map_at(net))); + } else { + if (accept_p != nullptr) + *accept_p = importer->net_map_at(net); + if (reject_p != nullptr) + *reject_p = module->Not(NEW_ID, importer->net_map_at(net)); + } } else if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION || From a1dd794ff883286dcd71c73fc21a701402e1078a Mon Sep 17 00:00:00 2001 From: YRabbit Date: Sat, 22 Apr 2023 17:10:53 +1000 Subject: [PATCH 06/17] gowin: Add all the primitives. Use selected data (names, ports and parameters) from vendor file for GW1N series primitives. Signed-off-by: YRabbit --- techlibs/gowin/Makefile.inc | 1 + techlibs/gowin/cells_xtra.py | 76 ++ techlibs/gowin/cells_xtra.v | 2003 +++++++++++++++++++++++++++++++++ techlibs/gowin/synth_gowin.cc | 1 + 4 files changed, 2081 insertions(+) create mode 100644 techlibs/gowin/cells_xtra.py create mode 100644 techlibs/gowin/cells_xtra.v diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc index 4f3a33f36..0e24b91e5 100644 --- a/techlibs/gowin/Makefile.inc +++ b/techlibs/gowin/Makefile.inc @@ -3,6 +3,7 @@ OBJS += techlibs/gowin/synth_gowin.o $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v)) +$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt)) diff --git a/techlibs/gowin/cells_xtra.py b/techlibs/gowin/cells_xtra.py new file mode 100644 index 000000000..4d117e428 --- /dev/null +++ b/techlibs/gowin/cells_xtra.py @@ -0,0 +1,76 @@ +#!/usr/bin/env python3 + +# Base on Nexus cells_xtra.py + +from argparse import ArgumentParser +import os.path +from enum import Enum, auto +import sys +import re + +class State(Enum): + OUTSIDE = auto() + IN_MODULE = auto() + IN_PARAMETER = auto() + +_skip = { 'ALU', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE', + 'DFFNE', 'DFFNP', 'DFFNPE', 'DFFNR', 'DFFNRE', 'DFFNS', 'DFFNSE', + 'DFFP', 'DFFPE', 'DFFR', 'DFFRE', 'DFFS', 'DFFSE', 'DP', 'DPX9', + 'ELVDS_OBUF', 'GND', 'GSR', 'IBUF', 'IDDR', 'IDDRC', 'IDES10', + 'IDES16', 'IDES4', 'IDES8', 'IOBUF', 'IVIDEO', 'LUT1', 'LUT2', + 'LUT3', 'LUT4', 'MUX2', 'MUX2_LUT5', 'MUX2_LUT6', 'MUX2_LUT7', + 'MUX2_LUT8', 'OBUF', 'ODDR', 'ODDRC', 'OSC', 'OSCF', 'OSCH', + 'OSCO', 'OSCW', 'OSCZ', 'OSER10', 'OSER16', 'OSER10', 'OSER4', + 'OSER8', 'OVIDEO', 'PLLVR', 'RAM16S1', 'RAM16S2', 'RAM16S4', + 'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP', + 'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC' + } +def xtract_cells_decl(dir, fout): + fname = os.path.join(dir, 'prim_sim.v') + with open(fname) as f: + state = State.OUTSIDE + for l in f: + l, _, comment = l.partition('//') + if l.startswith("module "): + cell_name = l[7:l.find('(')].strip() + if cell_name not in _skip: + state = State.IN_MODULE + fout.write(f'\nmodule {cell_name} (...);\n') + elif l.startswith(('input', 'output', 'inout')) and state == State.IN_MODULE: + fout.write(l) + if l[-1] != '\n': + fout.write('\n') + elif l.startswith('parameter') and state == State.IN_MODULE: + fout.write(l) + if l.rstrip()[-1] == ',': + state = State.IN_PARAMETER + if l[-1] != '\n': + fout.write('\n') + elif state == State.IN_PARAMETER: + fout.write(l) + if l.rstrip()[-1] == ';': + state = State.IN_MODULE + if l[-1] != '\n': + fout.write('\n') + elif l.startswith('endmodule') and state == State.IN_MODULE: + state = State.OUTSIDE + fout.write('endmodule\n') + if l[-1] != '\n': + fout.write('\n') + +if __name__ == '__main__': + parser = ArgumentParser(description='Extract Gowin blackbox cell definitions.') + parser.add_argument('gowin_dir', nargs='?', default='/opt/gowin/') + args = parser.parse_args() + + dirs = [ + os.path.join(args.gowin_dir, 'IDE/simlib/gw1n/'), + ] + + with open('cells_xtra.v', 'w') as fout: + fout.write('// Created by cells_xtra.py\n') + fout.write('\n') + for dir in dirs: + if not os.path.isdir(dir): + print(f'{dir} is not a directory') + xtract_cells_decl(dir, fout) diff --git a/techlibs/gowin/cells_xtra.v b/techlibs/gowin/cells_xtra.v new file mode 100644 index 000000000..4b89b8098 --- /dev/null +++ b/techlibs/gowin/cells_xtra.v @@ -0,0 +1,2003 @@ +// Created by cells_xtra.py + + +module MUX2_MUX8 (...); +input I0,I1; +input S0; +output O; +endmodule + + +module MUX2_MUX16 (...); +input I0,I1; +input S0; +output O; +endmodule + + +module MUX2_MUX32 (...); +input I0,I1; +input S0; +output O; +endmodule + + +module MUX4 (...); +input I0, I1, I2, I3; +input S0, S1; +output O; +endmodule + + +module MUX8 (...); +input I0, I1, I2, I3, I4, I5, I6, I7; +input S0, S1, S2; +output O; +endmodule + + +module MUX16 (...); +input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15; +input S0, S1, S2, S3; +output O; +endmodule + +module MUX32 (...); +input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31; +input S0, S1, S2, S3, S4; +output O; +endmodule + +module LUT5 (...); +parameter INIT = 32'h00000000; +input I0, I1, I2, I3, I4; +output F; +endmodule + + +module LUT6 (...); +parameter INIT = 64'h0000_0000_0000_0000; +input I0, I1, I2, I3, I4, I5; +output F; +endmodule + + +module LUT7 (...); +parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000; +input I0, I1, I2, I3, I4, I5, I6; +output F; +endmodule + + +module LUT8 (...); +parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; +input I0, I1, I2, I3, I4, I5, I6, I7; +output F; +endmodule + + +module DL (...); +input D, G; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLE (...); +input D, G, CE; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLC (...); +input D, G, CLEAR; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLCE (...); +input D, G, CLEAR, CE; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLP (...); +input D, G, PRESET; +output Q; +parameter INIT = 1'b1; +endmodule + + +module DLPE (...); +input D, G, PRESET, CE; +output Q; +parameter INIT = 1'b1; +endmodule + + +module DLN (...); +input D, G; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLNE (...); +input D, G, CE; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLNC (...); +input D, G, CLEAR; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLNCE (...); +input D, G, CLEAR, CE; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLNP (...); +input D, G, PRESET; +output Q; +parameter INIT = 1'b1; +endmodule + + +module DLNPE (...); +input D, G, PRESET, CE; +output Q; +parameter INIT = 1'b1; +endmodule + + +module INV (...); +input I; +output O; +endmodule + + +module IODELAY (...); +parameter C_STATIC_DLY = 0; +input DI; +input SDTAP; +input SETN; +input VALUE; +output DF; +output DO; +endmodule + + +module IEM (...); +parameter WINSIZE = "SMALL"; +parameter GSREN = "false"; +parameter LSREN = "true"; +input D, CLK, RESET, MCLK; +output LAG, LEAD; +endmodule + + +module ROM16 (...); +parameter INIT_0 = 16'h0000; +input [3:0] AD; +output DO; +endmodule + + +module ROM (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input WRE; +input [13:0] AD; +input [2:0] BLKSEL; +output [31:0] DO; +endmodule + + +module ROMX9 (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input WRE; +input [13:0] AD; +input [2:0] BLKSEL; +output [35:0] DO; +endmodule + + +module rSDP (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 32; +parameter BIT_WIDTH_1 = 32; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCE; +input RESETA, RESETB; +input [13:0] ADA, ADB; +input [31:0] DI; +input [2:0] BLKSEL; +output [31:0] DO; +endmodule + + +module rSDPX9 (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 36; +parameter BIT_WIDTH_1 = 36; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCE; +input RESETA, RESETB; +input [13:0] ADA, ADB; +input [2:0] BLKSEL; +input [35:0] DI; +output [35:0] DO; +endmodule + + +module rROM (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input [13:0] AD; +input [2:0] BLKSEL; +output [31:0] DO; +endmodule + + +module rROMX9 (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input [13:0] AD; +input [2:0] BLKSEL; +output [35:0] DO; +endmodule + + +module pROM (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input [13:0] AD; +output [31:0] DO; +endmodule + + +module pROMX9 (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input [13:0] AD; +output [35:0] DO; +endmodule + + +module SDPB (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 32; +parameter BIT_WIDTH_1 = 32; +parameter BLK_SEL_0 = 3'b000; +parameter BLK_SEL_1 = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCE; +input RESETA, RESETB; +input [13:0] ADA, ADB; +input [31:0] DI; +input [2:0] BLKSELA, BLKSELB; +output [31:0] DO; +endmodule + + +module SDPX9B (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 36; +parameter BIT_WIDTH_1 = 36; +parameter BLK_SEL_0 = 3'b000; +parameter BLK_SEL_1 = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCE; +input RESETA, RESETB; +input [13:0] ADA, ADB; +input [2:0] BLKSELA, BLKSELB; +input [35:0] DI; +output [35:0] DO; +endmodule + + +module DPB (...); +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 16; +parameter BIT_WIDTH_1 = 16; +parameter BLK_SEL_0 = 3'b000; +parameter BLK_SEL_1 = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; +input [13:0] ADA, ADB; +input [2:0] BLKSELA, BLKSELB; +input [15:0] DIA, DIB; +output [15:0] DOA, DOB; +endmodule + + +module DPX9B (...); +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 18; +parameter BIT_WIDTH_1 = 18; +parameter BLK_SEL_0 = 3'b000; +parameter BLK_SEL_1 = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; +input [13:0] ADA, ADB; +input [17:0] DIA, DIB; +input [2:0] BLKSELA, BLKSELB; +output [17:0] DOA, DOB; +endmodule + + +module PADD18 (...); +input [17:0] A; +input [17:0] B; +input ASEL; +input CE,CLK,RESET; +input [17:0] SI,SBI; +output [17:0] SO,SBO; +output [17:0] DOUT; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; +parameter SOREG = 1'b0; +endmodule + +module PADD9 (...); +input [8:0] A; +input [8:0] B; +input ASEL; +input CE,CLK,RESET; +input [8:0] SI,SBI; +output [8:0] SO,SBO; +output [8:0] DOUT; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; +parameter SOREG = 1'b0; +endmodule + +module MULT9X9 (...); +input [8:0] A,SIA; +input [8:0] B,SIB; +input ASIGN,BSIGN; +input ASEL,BSEL; +input CE; +input CLK; +input RESET; +output [17:0] DOUT; +output [8:0] SOA,SOB; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter OUT_REG = 1'b0; +parameter PIPE_REG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter SOA_REG = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +endmodule + +module MULT18X18 (...); +input [17:0] A,SIA; +input [17:0] B,SIB; +input ASIGN,BSIGN; +input ASEL,BSEL; +input CE; +input CLK; +input RESET; +output [35:0] DOUT; +output [17:0] SOA,SOB; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter OUT_REG = 1'b0; +parameter PIPE_REG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter SOA_REG = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +endmodule + +module MULT36X36 (...); +input [35:0] A; +input [35:0] B; +input ASIGN,BSIGN; +input CE; +input CLK; +input RESET; +output [71:0] DOUT; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter OUT0_REG = 1'b0; +parameter OUT1_REG = 1'b0; +parameter PIPE_REG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +endmodule + +module MULTALU36X18 (...); +input [17:0] A; +input [35:0] B; +input [53:0] C; +input ASIGN,BSIGN,ACCLOAD; +input CE; +input CLK; +input RESET; +input [54:0] CASI; +output [53:0] DOUT; +output [54:0] CASO; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter CREG = 1'b0; +parameter OUT_REG = 1'b0; +parameter PIPE_REG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter ACCLOAD_REG0 = 1'b0; +parameter ACCLOAD_REG1 = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +parameter MULTALU36X18_MODE = 0; +parameter C_ADD_SUB = 1'b0; +endmodule + +module MULTADDALU18X18 (...); +input [17:0] A0; +input [17:0] B0; +input [17:0] A1; +input [17:0] B1; +input [53:0] C; +input [17:0] SIA, SIB; +input [1:0] ASIGN, BSIGN; +input [1:0] ASEL, BSEL; +input [54:0] CASI; +input CE; +input CLK; +input RESET; +input ACCLOAD; +output [53:0] DOUT; +output [54:0] CASO; +output [17:0] SOA, SOB; +parameter A0REG = 1'b0; +parameter A1REG = 1'b0; +parameter B0REG = 1'b0; +parameter B1REG = 1'b0; +parameter CREG = 1'b0; +parameter PIPE0_REG = 1'b0; +parameter PIPE1_REG = 1'b0; +parameter OUT_REG = 1'b0; +parameter ASIGN0_REG = 1'b0; +parameter ASIGN1_REG = 1'b0; +parameter ACCLOAD_REG0 = 1'b0; +parameter ACCLOAD_REG1 = 1'b0; +parameter BSIGN0_REG = 1'b0; +parameter BSIGN1_REG = 1'b0; +parameter SOA_REG = 1'b0; +parameter B_ADD_SUB = 1'b0; +parameter C_ADD_SUB = 1'b0; +parameter MULTADDALU18X18_MODE = 0; +parameter MULT_RESET_MODE = "SYNC"; +endmodule + +module MULTALU18X18 (...); +input [17:0] A, B; +input CLK,CE,RESET; +input ASIGN, BSIGN; +input ACCLOAD,DSIGN; +input [53:0] C,D; +input [54:0] CASI; +output [53:0] DOUT; +output [54:0] CASO; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter CREG = 1'b0; +parameter DREG = 1'b0; +parameter DSIGN_REG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter ACCLOAD_REG0 = 1'b0; +parameter ACCLOAD_REG1 = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +parameter PIPE_REG = 1'b0; +parameter OUT_REG = 1'b0; +parameter B_ADD_SUB = 1'b0; +parameter C_ADD_SUB = 1'b0; +parameter MULTALU18X18_MODE = 0; +endmodule + +module ALU54D (...); +input [53:0] A, B; +input ASIGN,BSIGN; +input ACCLOAD; +input [54:0] CASI; +input CLK, CE, RESET; +output [53:0] DOUT; +output [54:0] CASO; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter ACCLOAD_REG = 1'b0; +parameter OUT_REG = 1'b0; +parameter B_ADD_SUB = 1'b0; +parameter C_ADD_SUB = 1'b0; +parameter ALUD_MODE = 0; +parameter ALU_RESET_MODE = "SYNC"; +endmodule + +module BUFG (...); +output O; +input I; +endmodule + + +module BUFS (...); +output O; +input I; +endmodule + + +module PLL (...); +input CLKIN; +input CLKFB; +input RESET; +input RESET_P; +input RESET_I; +input RESET_S; +input [5:0] FBDSEL; +input [5:0] IDSEL; +input [5:0] ODSEL; +input [3:0] PSDA,FDLY; +input [3:0] DUTYDA; +output CLKOUT; +output LOCK; +output CLKOUTP; +output CLKOUTD; +output CLKOUTD3; +parameter FCLKIN = "100.0"; +parameter DYN_IDIV_SEL= "false"; +parameter IDIV_SEL = 0; +parameter DYN_FBDIV_SEL= "false"; +parameter FBDIV_SEL = 0; +parameter DYN_ODIV_SEL= "false"; +parameter ODIV_SEL = 8; +parameter PSDA_SEL= "0000"; +parameter DYN_DA_EN = "false"; +parameter DUTYDA_SEL= "1000"; +parameter CLKOUT_FT_DIR = 1'b1; +parameter CLKOUTP_FT_DIR = 1'b1; +parameter CLKOUT_DLY_STEP = 0; +parameter CLKOUTP_DLY_STEP = 0; +parameter CLKFB_SEL = "internal"; +parameter CLKOUT_BYPASS = "false"; +parameter CLKOUTP_BYPASS = "false"; +parameter CLKOUTD_BYPASS = "false"; +parameter DYN_SDIV_SEL = 2; +parameter CLKOUTD_SRC = "CLKOUT"; +parameter CLKOUTD3_SRC = "CLKOUT"; +parameter DEVICE = "GW1N-4"; +endmodule + +module TLVDS_IBUF (...); +output O; +input I, IB; +endmodule + +module TLVDS_TBUF (...); +output O, OB; +input I, OEN; +endmodule + +module TLVDS_IOBUF (...); +output O; +inout IO, IOB; +input I, OEN; +endmodule + +module ELVDS_IBUF (...); +output O; +input I, IB; +endmodule + +module ELVDS_TBUF (...); +output O, OB; +input I, OEN; +endmodule + +module ELVDS_IOBUF (...); +output O; +inout IO, IOB; +input I, OEN; +endmodule + +module MIPI_IBUF (...); +output OH, OL, OB; +inout IO, IOB; +input I, IB; +input OEN, OENB; +input HSREN; +endmodule + +module MIPI_IBUF_HS (...); +output OH; +input I, IB; +endmodule + +module MIPI_IBUF_LP (...); +output OL; +output OB; +input I; +input IB; +endmodule + +module MIPI_OBUF (...); +output O, OB; +input I, IB, MODESEL; +endmodule + +module MIPI_OBUF_A (...); +output O, OB; +input I, IB, IL, MODESEL; +endmodule + +module I3C_IOBUF (...); +output O; +inout IO; +input I, MODESEL; +endmodule + +module CLKDIV (...); +input HCLKIN; +input RESETN; +input CALIB; +output CLKOUT; +parameter DIV_MODE = "2"; +parameter GSREN = "false"; +endmodule + +module DHCEN (...); +input CLKIN,CE; +output CLKOUT; +endmodule + +module DLL (...); +input CLKIN; +input STOP; +input UPDNCNTL; +input RESET; +output [7:0]STEP; +output LOCK; +parameter DLL_FORCE = 0; +parameter CODESCAL="000"; +parameter SCAL_EN="true"; +parameter DIV_SEL = 1'b0; +endmodule + +module DLLDLY (...); +input CLKIN; +input [7:0] DLLSTEP; +input DIR,LOADN,MOVE; +output CLKOUT; +output FLAG; +parameter DLL_INSEL = 1'b1; +parameter DLY_SIGN = 1'b0; +parameter DLY_ADJ = 0; +endmodule + +module FLASH96K (...); +input [5:0] RA,CA,PA; +input [3:0] MODE; +input [1:0] SEQ; +input ACLK,PW,RESET,PE,OE; +input [1:0] RMODE,WMODE; +input [1:0] RBYTESEL,WBYTESEL; +input [31:0] DIN; +output [31:0] DOUT; +endmodule + +module FLASH256K (...); +input[6:0]XADR; +input[5:0]YADR; +input XE,YE,SE; +input ERASE,PROG,NVSTR; +input [31:0] DIN; +output reg [31:0] DOUT; +parameter IDLE = 4'd0, + ERA_S1 = 4'd1, + ERA_S2 = 4'd2, + ERA_S3 = 4'd3, + ERA_S4 = 4'd4, + ERA_S5 = 4'd5, + PRO_S1 = 4'd6, + PRO_S2 = 4'd7, + PRO_S3 = 4'd8, + PRO_S4 = 4'd9, + PRO_S5 = 4'd10, + RD_S1 = 4'd11, + RD_S2 = 4'd12; +endmodule + +module FLASH608K (...); +input[8:0]XADR; +input[5:0]YADR; +input XE,YE,SE; +input ERASE,PROG,NVSTR; +input [31:0] DIN; +output reg [31:0] DOUT; +parameter IDLE = 4'd0, + ERA_S1 = 4'd1, + ERA_S2 = 4'd2, + ERA_S3 = 4'd3, + ERA_S4 = 4'd4, + ERA_S5 = 4'd5, + PRO_S1 = 4'd6, + PRO_S2 = 4'd7, + PRO_S3 = 4'd8, + PRO_S4 = 4'd9, + PRO_S5 = 4'd10, + RD_S1 = 4'd11, + RD_S2 = 4'd12; +endmodule + +module DCS (...); +input CLK0, CLK1, CLK2, CLK3, SELFORCE; +input [3:0] CLKSEL; +output CLKOUT; +endmodule + +module DQCE (...); +input CLKIN; +input CE; +output CLKOUT; +endmodule + +module FLASH128K (...); +input [31:0] DIN; +input [14:0] ADDR; +input CS,AE,OE; +input PCLK; +input PROG, SERA, MASE; +input NVSTR; +input IFREN; +input RESETN; +output [31:0] DOUT; +output TBIT; +parameter IDLE = 4'd0, + READ_S1 = 4'd1, + READ_S2 = 4'd2, + PROG_S1 = 4'd3, + PROG_S2 = 4'd4, + PROG_S3 = 4'd5, + PROG_S4 = 4'd6, + SERA_S1 = 4'd7, + SERA_S2 = 4'd8, + SERA_S3 = 4'd9, + SERA_S4 = 4'd10, + MASE_S1 = 4'd11, + MASE_S2 = 4'd12, + MASE_S3 = 4'd13, + MASE_S4 = 4'd14; +endmodule + +module MCU (...); +endmodule + +module USB20_PHY (...); +parameter DATABUS16_8 = 1'b0; +parameter ADP_PRBEN = 1'b0; +parameter TEST_MODE = 5'b00000; +parameter HSDRV1 = 1'b0; +parameter HSDRV0 = 1'b0; +parameter CLK_SEL = 1'b0; +parameter M = 4'b0000; +parameter N = 6'b101000; +parameter C = 2'b01; +parameter FOC_LOCK = 1'b0; +input [15:0] DATAIN; +input TXVLD; +input TXVLDH; +input RESET; +input SUSPENDM; +input [1:0] XCVRSEL; +input TERMSEL; +input [1:0] OPMODE; +output [15:0] DATAOUT; +output TXREADY; +output RXACTIVE; +output RXVLD; +output RXVLDH; +output CLK; +output RXERROR; +inout DP; +inout DM; +output [1:0] LINESTATE; +input IDPULLUP; +input DPPD; +input DMPD; +input CHARGVBUS; +input DISCHARGVBUS; +input TXBITSTUFFEN; +input TXBITSTUFFENH; +input TXENN; +input TXDAT; +input TXSE0; +input FSLSSERIAL; +output HOSTDIS; +output IDDIG; +output ADPPRB; +output ADPSNS; +output SESSVLD; +output VBUSVLD; +output RXDP; +output RXDM; +output RXRCV; +output LBKERR; +output CLKRDY; +input INTCLK; +inout ID; +inout VBUS; +inout REXT; +input XIN; +inout XOUT; +input TEST; +output CLK480PAD; +input SCANCLK; +input SCANEN; +input SCANMODE; +input TRESETN; +input SCANIN1; +output SCANOUT1; +input SCANIN2; +output SCANOUT2; +input SCANIN3; +output SCANOUT3; +input SCANIN4; +output SCANOUT4; +input SCANIN5; +output SCANOUT5; +input SCANIN6; +output SCANOUT6; +endmodule + +module ADC (...); +endmodule + +module BANDGAP (...); +input BGEN; +endmodule + +module CLKDIV2 (...); +parameter GSREN = "false"; +input HCLKIN, RESETN; +output CLKOUT; +endmodule + +module DCC (...); +output CLKOUT; +input CLKIN; +parameter DCC_EN = 1'b1; +parameter FCLKIN = 50.0; +endmodule + +module DHCENC (...); +input CLKIN, CE; +output CLKOUT, CLKOUTN; +endmodule + +module EMCU (...); +endmodule + +module FLASH64K (...); +input[4:0]XADR; +input[5:0]YADR; +input XE,YE,SE; +input ERASE,PROG,NVSTR; +input SLEEP; +input [31:0] DIN; +output reg [31:0] DOUT; +parameter IDLE = 4'd0, + ERA_S1 = 4'd1, + ERA_S2 = 4'd2, + ERA_S3 = 4'd3, + ERA_S4 = 4'd4, + ERA_S5 = 4'd5, + PRO_S1 = 4'd6, + PRO_S2 = 4'd7, + PRO_S3 = 4'd8, + PRO_S4 = 4'd9, + PRO_S5 = 4'd10, + RD_S1 = 4'd11, + RD_S2 = 4'd12; +endmodule + +module FLASH64KZ (...); +input[4:0]XADR; +input[5:0]YADR; +input XE,YE,SE; +input ERASE,PROG,NVSTR; +input [31:0] DIN; +output reg [31:0] DOUT; +parameter IDLE = 4'd0, + ERA_S1 = 4'd1, + ERA_S2 = 4'd2, + ERA_S3 = 4'd3, + ERA_S4 = 4'd4, + ERA_S5 = 4'd5, + PRO_S1 = 4'd6, + PRO_S2 = 4'd7, + PRO_S3 = 4'd8, + PRO_S4 = 4'd9, + PRO_S5 = 4'd10, + RD_S1 = 4'd11, + RD_S2 = 4'd12; +endmodule + +module I3C (...); +parameter ADDRESS = 7'b0000000; +input LGYS, CMS, ACS, AAS, STOPS, STRTS; +output LGYO, CMO, ACO, AAO, SIO, STOPO, STRTO; +input LGYC, CMC, ACC, AAC, SIC, STOPC, STRTC; +input STRTHDS, SENDAHS, SENDALS, ACKHS; +input ACKLS, STOPSUS, STOPHDS, SENDDHS; +input SENDDLS, RECVDHS, RECVDLS, ADDRS; +output PARITYERROR; +input [7:0] DI; +output [7:0] DOBUF; +output [7:0] DO; +output [7:0] STATE; +input SDAI, SCLI; +output SDAO, SCLO; +output SDAOEN, SCLOEN; +output SDAPULLO, SCLPULLO; +output SDAPULLOEN, SCLPULLOEN; +input CE, RESET, CLK; +endmodule + +module IODELAYA (...); +parameter C_STATIC_DLY = 0; +input DI; +input SDTAP; +input SETN; +input VALUE; +output DF; +output DO; +endmodule + +module IODELAYC (...); +parameter C_STATIC_DLY = 0; +parameter DYN_DA_SEL = "false"; +parameter DA_SEL = 2'b00; +input DI; +input SDTAP; +input SETN; +input VALUE; +input [1:0] DASEL; +input [1:0] DAADJ; +output DF; +output DO; +output DAO; +endmodule + + +module SPMI (...); +parameter FUNCTION_CTRL = 7'b0000000; +parameter MSID_CLKSEL = 7'b0000000; +parameter RESPOND_DELAY = 4'b0000; +parameter SCLK_NORMAL_PERIOD = 7'b0000000; +parameter SCLK_LOW_PERIOD = 7'b0000000; +parameter CLK_FREQ = 7'b0000000; +parameter SHUTDOWN_BY_ENABLE = 1'b0; +input CLKEXT, ENEXT; +inout SDATA, SCLK; +input CLK, CE, RESETN, LOCRESET; +input PA, SA, CA; +input [3:0] ADDRI; +input [7:0] DATAI; +output [3:0] ADDRO; +output [7:0] DATAO; +output [15:0] STATE; +output [3:0] CMD; +endmodule + +module IODELAYB (...); +parameter C_STATIC_DLY = 0; +parameter DELAY_MUX = 2'b00; +parameter DA_SEL = 2'b00; +input DI; +input SDTAP; +input SETN; +input VALUE; +input [1:0] DAADJ; +output DF; +output DO; +output DAO; +endmodule + + +module PLLO (...); +input CLKIN; +input CLKFB; +input RESET; +input RESET_P; +input RESET_I; +input RESET_S; +input [5:0] FBDSEL; +input [5:0] IDSEL; +input [6:0] ODSELA; +input [6:0] ODSELB; +input [6:0] ODSELC; +input [6:0] ODSELD; +input [3:0] DTA; +input [3:0] DTB; +input [4:0] ICPSEL; +input [2:0] LPFRES; +input [1:0] PSSEL; +input PSDIR; +input PSPULSE; +input ENCLKA; +input ENCLKB; +input ENCLKC; +input ENCLKD; +output LOCK; +output CLKOUTA; +output CLKOUTB; +output CLKOUTC; +output CLKOUTD; +parameter FCLKIN = "100.0"; +parameter DYN_IDIV_SEL= "FALSE"; +parameter IDIV_SEL = 0; +parameter DYN_FBDIV_SEL= "FALSE"; +parameter FBDIV_SEL = 0; +parameter DYN_ODIVA_SEL= "FALSE"; +parameter ODIVA_SEL = 6; +parameter DYN_ODIVB_SEL= "FALSE"; +parameter ODIVB_SEL = 6; +parameter DYN_ODIVC_SEL= "FALSE"; +parameter ODIVC_SEL = 6; +parameter DYN_ODIVD_SEL= "FALSE"; +parameter ODIVD_SEL = 6; +parameter CLKOUTA_EN = "TRUE"; +parameter CLKOUTB_EN = "TRUE"; +parameter CLKOUTC_EN = "TRUE"; +parameter CLKOUTD_EN = "TRUE"; +parameter DYN_DTA_SEL = "FALSE"; +parameter DYN_DTB_SEL = "FALSE"; +parameter CLKOUTA_DT_DIR = 1'b1; +parameter CLKOUTB_DT_DIR = 1'b1; +parameter CLKOUTA_DT_STEP = 0; +parameter CLKOUTB_DT_STEP = 0; +parameter CLKA_IN_SEL = 2'b00; +parameter CLKA_OUT_SEL = 1'b0; +parameter CLKB_IN_SEL = 2'b00; +parameter CLKB_OUT_SEL = 1'b0; +parameter CLKC_IN_SEL = 2'b00; +parameter CLKC_OUT_SEL = 1'b0; +parameter CLKD_IN_SEL = 2'b00; +parameter CLKD_OUT_SEL = 1'b0; +parameter CLKFB_SEL = "INTERNAL"; +parameter DYN_DPA_EN = "FALSE"; +parameter DYN_PSB_SEL = "FALSE"; +parameter DYN_PSC_SEL = "FALSE"; +parameter DYN_PSD_SEL = "FALSE"; +parameter PSB_COARSE = 1; +parameter PSB_FINE = 0; +parameter PSC_COARSE = 1; +parameter PSC_FINE = 0; +parameter PSD_COARSE = 1; +parameter PSD_FINE = 0; +parameter DTMS_ENB = "FALSE"; +parameter DTMS_ENC = "FALSE"; +parameter DTMS_END = "FALSE"; +parameter RESET_I_EN = "FALSE"; +parameter RESET_S_EN = "FALSE"; +parameter DYN_ICP_SEL= "FALSE"; +parameter ICP_SEL = 5'bXXXXX; +parameter DYN_RES_SEL= "FALSE"; +parameter LPR_REF = 7'bXXXXXXX; +endmodule + +module DCCG (...); +output CLKOUT; +input CLKIN; +parameter DCC_MODE = 2'b00; +parameter FCLKIN = 50.0; +endmodule + +module FLASH96KA (...); +input[5:0]XADR; +input[5:0]YADR; +input XE,YE,SE; +input ERASE,PROG,NVSTR; +input [31:0] DIN; +input SLEEP; +output reg [31:0] DOUT; +parameter IDLE = 4'd0, + ERA_S1 = 4'd1, + ERA_S2 = 4'd2, + ERA_S3 = 4'd3, + ERA_S4 = 4'd4, + ERA_S5 = 4'd5, + PRO_S1 = 4'd6, + PRO_S2 = 4'd7, + PRO_S3 = 4'd8, + PRO_S4 = 4'd9, + PRO_S5 = 4'd10, + RD_S1 = 4'd11, + RD_S2 = 4'd12; +endmodule + +module MIPI_DPHY_RX (...); +output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD; +output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD; +output DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P; +output DI_LPRXCK_N, DI_LPRXCK_P; +output RX_CLK_O; +output DESKEW_ERROR; +inout CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P; +input LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; +input HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3; +input D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN; +input HSRX_EN_CK; +input HS_8BIT_MODE; +input RX_CLK_1X; +input RX_INVERT; +input LALIGN_EN; +input WALIGN_BY; +input DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P; +input DO_LPTXCK_N, DO_LPTXCK_P; +input LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3; +input BYTE_LENDIAN; +input HSRX_STOP; +input LPRX_ULP_LN0, LPRX_ULP_LN1, LPRX_ULP_LN2, LPRX_ULP_LN3, LPRX_ULP_CK; +input PWRON; +input RESET; +input [2:0] DESKEW_LNSEL; +input [7:0] DESKEW_MTH; +input [6:0] DESKEW_OWVAL; +input DESKEW_REQ; +input DRST_N; +input ONE_BYTE0_MATCH; +input WORD_LENDIAN; +input [2:0] FIFO_RD_STD; +parameter ALIGN_BYTE = 8'b10111000; +parameter MIPI_LANE0_EN = 1'b0; +parameter MIPI_LANE1_EN = 1'b0; +parameter MIPI_LANE2_EN = 1'b0; +parameter MIPI_LANE3_EN = 1'b0; +parameter MIPI_CK_EN = 1'b1; +parameter SYNC_CLK_SEL = 1'b1; +endmodule + +module CLKDIVG (...); +input CLKIN; +input RESETN; +input CALIB; +output CLKOUT; +parameter DIV_MODE = "2"; +parameter GSREN = "false"; +endmodule diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 0dffdf498..3b9d7424a 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -207,6 +207,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("begin")) { run("read_verilog -specify -lib +/gowin/cells_sim.v"); + run("read_verilog -specify -lib +/gowin/cells_xtra.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } From 7bff8b63b366e1e9c8308a235133600afac757e8 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 25 Apr 2023 12:39:00 +0200 Subject: [PATCH 07/17] rename: Fix renaming cells in -witness mode This was renaming cells while iterating over them which would always cause an assertion failure. Apparently having to rename cells to make all witness signals public is rarely required, so this slipped through. --- passes/cmds/rename.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 45576c91c..6bd317ed0 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -116,6 +116,8 @@ static bool rename_witness(RTLIL::Design *design, dict &ca } cache.emplace(module, -1); + std::vector> renames; + bool has_witness_signals = false; for (auto cell : module->cells()) { @@ -130,8 +132,9 @@ static bool rename_witness(RTLIL::Design *design, dict &ca c = '_'; auto new_id = module->uniquify("\\_witness_." + name); cell->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 }); - module->rename(cell, new_id); + renames.emplace_back(cell, new_id); } + break; } if (cell->type.in(ID($anyconst), ID($anyseq), ID($anyinit), ID($allconst), ID($allseq))) { @@ -155,6 +158,9 @@ static bool rename_witness(RTLIL::Design *design, dict &ca } } } + for (auto rename : renames) { + module->rename(rename.first, rename.second); + } cache[module] = has_witness_signals; return has_witness_signals; From 30f1d109484141c9fd0b398bef59f6883af35aa8 Mon Sep 17 00:00:00 2001 From: Ralf Fuest Date: Mon, 1 May 2023 17:56:41 +0200 Subject: [PATCH 08/17] gowin: Fix X output of $alu techmap --- techlibs/gowin/arith_map.v | 2 +- tests/arch/gowin/compare.v | 20 ++++++++++++++++++++ tests/arch/gowin/compare.ys | 9 +++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 tests/arch/gowin/compare.v create mode 100644 tests/arch/gowin/compare.ys diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v index 2d48fa752..828bb35b8 100644 --- a/techlibs/gowin/arith_map.v +++ b/techlibs/gowin/arith_map.v @@ -62,6 +62,6 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO); .SUM(Y[i]) ); end endgenerate - assign X = AA ^ BB; + assign X = AA ^ BB ^ {Y_WIDTH{BI}}; endmodule diff --git a/tests/arch/gowin/compare.v b/tests/arch/gowin/compare.v new file mode 100644 index 000000000..0ed3c2fa4 --- /dev/null +++ b/tests/arch/gowin/compare.v @@ -0,0 +1,20 @@ +module top +( + input [4:0] x, + input [4:0] y, + + output lt, + output le, + output gt, + output ge, + output eq, + output ne +); + + assign lt = x < y; + assign le = x <= y; + assign gt = x > y; + assign ge = x >= y; + assign eq = x == y; + assign ne = x != y; +endmodule diff --git a/tests/arch/gowin/compare.ys b/tests/arch/gowin/compare.ys new file mode 100644 index 000000000..a3aba6dea --- /dev/null +++ b/tests/arch/gowin/compare.ys @@ -0,0 +1,9 @@ +read_verilog compare.v +hierarchy -top top +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 5 t:ALU + + From 572c8df9a86e3040d13b403976f0c23191c99d78 Mon Sep 17 00:00:00 2001 From: Aki Van Ness Date: Wed, 3 May 2023 02:22:46 -0400 Subject: [PATCH 09/17] plugin: Re-vamped how plugin lookup was done to make it more consistent with the rest of yosys, and prevented a case where you could end up with `.so.so` on the end --- passes/cmds/plugin.cc | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 3a1ae2850..85aae239d 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -21,12 +21,12 @@ #ifdef YOSYS_ENABLE_PLUGINS # include +# include +# include #endif #ifdef WITH_PYTHON -# include # include -# include #endif YOSYS_NAMESPACE_BEGIN @@ -41,20 +41,18 @@ std::map loaded_plugin_aliases; void load_plugin(std::string filename, std::vector aliases) { std::string orig_filename = filename; + rewrite_filename(filename); + boost::filesystem::path full_path(filename); - if (filename.find('/') == std::string::npos) - filename = "./" + filename; #ifdef WITH_PYTHON - if (!loaded_plugins.count(filename) && !loaded_python_plugins.count(filename)) { + if (!loaded_plugins.count(orig_filename) && !loaded_python_plugins.count(orig_filename)) { #else - if (!loaded_plugins.count(filename)) { + if (!loaded_plugins.count(orig_filename)) { #endif #ifdef WITH_PYTHON - boost::filesystem::path full_path(filename); - if(strcmp(full_path.extension().c_str(), ".py") == 0) { std::string path(full_path.parent_path().c_str()); @@ -75,10 +73,23 @@ void load_plugin(std::string filename, std::vector aliases) #endif void *hdl = dlopen(filename.c_str(), RTLD_LAZY|RTLD_LOCAL); - if (hdl == NULL && orig_filename.find('/') == std::string::npos) - hdl = dlopen((proc_share_dirname() + "plugins/" + orig_filename + ".so").c_str(), RTLD_LAZY|RTLD_LOCAL); + + // We were unable to open the file, try to do so from the plugin directory + if (hdl == NULL && filename.find('/') == std::string::npos) { + hdl = dlopen([filename]() { + std::string new_path = proc_share_dirname() + "plugins/" + filename; + + // Check if we need to append .so + if (new_path.find(".so") == std::string::npos) + new_path.append(".so"); + + return new_path; + }().c_str(), RTLD_LAZY|RTLD_LOCAL); + } + if (hdl == NULL) log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror()); + loaded_plugins[orig_filename] = hdl; Pass::init_register(); @@ -182,4 +193,3 @@ struct PluginPass : public Pass { } PluginPass; YOSYS_NAMESPACE_END - From bb240665b7da95687e60379c1a71dfb97c9cc820 Mon Sep 17 00:00:00 2001 From: Aki Van Ness Date: Wed, 3 May 2023 02:50:23 -0400 Subject: [PATCH 10/17] plugin: shuffled the `#ifdef WITH_PYTHON`'s around to un-tangle the code and pulled out the check for the `.py` extension so it will complain if you try to load a python extension without python support --- passes/cmds/plugin.cc | 93 ++++++++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 42 deletions(-) diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 85aae239d..08b4aa8c4 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -21,12 +21,12 @@ #ifdef YOSYS_ENABLE_PLUGINS # include -# include -# include #endif #ifdef WITH_PYTHON +# include # include +# include #endif YOSYS_NAMESPACE_BEGIN @@ -42,60 +42,69 @@ void load_plugin(std::string filename, std::vector aliases) { std::string orig_filename = filename; rewrite_filename(filename); - boost::filesystem::path full_path(filename); + + // Would something like this better be put in `rewrite_filename`? + if (filename.find("/") == std::string::npos) + filename = "./" + filename; #ifdef WITH_PYTHON - if (!loaded_plugins.count(orig_filename) && !loaded_python_plugins.count(orig_filename)) { + const bool is_loaded = loaded_plugins.count(orig_filename) && loaded_python_plugins.count(orig_filename); #else - if (!loaded_plugins.count(orig_filename)) { + const bool is_loaded = loaded_plugins.count(orig_filename); #endif - #ifdef WITH_PYTHON - - if(strcmp(full_path.extension().c_str(), ".py") == 0) + if (!is_loaded) { + // Check if we're loading a python script + if(filename.find(".py") != std::string::npos) { - std::string path(full_path.parent_path().c_str()); - filename = full_path.filename().c_str(); - filename = filename.substr(0,filename.size()-3); - PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str()); - PyErr_Print(); - PyObject *module_p = PyImport_ImportModule(filename.c_str()); - if(module_p == NULL) - { + #ifdef WITH_PYTHON + boost::filesystem::path full_path(filename); + std::string path(full_path.parent_path().c_str()); + filename = full_path.filename().c_str(); + filename = filename.substr(0,filename.size()-3); + PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str()); PyErr_Print(); - log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str()); - return; - } - loaded_python_plugins[orig_filename] = module_p; - Pass::init_register(); + PyObject *module_p = PyImport_ImportModule(filename.c_str()); + if(module_p == NULL) + { + PyErr_Print(); + log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str()); + return; + } + loaded_python_plugins[orig_filename] = module_p; + Pass::init_register(); + #else + log_error( + "\n This version of Yosys cannot load python plugins.\n" + " Ensure Yosys is built with Python support to do so.\n" + ); + #endif } else { - #endif + // Otherwise we assume it's a native plugin - void *hdl = dlopen(filename.c_str(), RTLD_LAZY|RTLD_LOCAL); + void *hdl = dlopen(filename.c_str(), RTLD_LAZY|RTLD_LOCAL); - // We were unable to open the file, try to do so from the plugin directory - if (hdl == NULL && filename.find('/') == std::string::npos) { - hdl = dlopen([filename]() { - std::string new_path = proc_share_dirname() + "plugins/" + filename; + // We were unable to open the file, try to do so from the plugin directory + if (hdl == NULL && orig_filename.find('/') == std::string::npos) { + hdl = dlopen([orig_filename]() { + std::string new_path = proc_share_dirname() + "plugins/" + orig_filename; - // Check if we need to append .so - if (new_path.find(".so") == std::string::npos) - new_path.append(".so"); + // Check if we need to append .so + if (new_path.find(".so") == std::string::npos) + new_path.append(".so"); + + return new_path; + }().c_str(), RTLD_LAZY|RTLD_LOCAL); + } + + if (hdl == NULL) + log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror()); + + loaded_plugins[orig_filename] = hdl; + Pass::init_register(); - return new_path; - }().c_str(), RTLD_LAZY|RTLD_LOCAL); } - - if (hdl == NULL) - log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror()); - - loaded_plugins[orig_filename] = hdl; - Pass::init_register(); - - #ifdef WITH_PYTHON - } - #endif } for (auto &alias : aliases) From 17cfc969ddfe800525dbeab272b53949846e28b8 Mon Sep 17 00:00:00 2001 From: Muthu Annamalai Date: Sun, 7 May 2023 06:19:02 +0000 Subject: [PATCH 11/17] [YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest --- passes/techmap/libparse.cc | 11 +++++++---- tests/liberty/issue3498_bad.lib | 8 ++++++++ 2 files changed, 15 insertions(+), 4 deletions(-) create mode 100755 tests/liberty/issue3498_bad.lib diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index 3d0ebaea3..1a1726f94 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -236,10 +236,13 @@ LibertyAst *LibertyParser::parse() if (tok == ':' && ast->value.empty()) { tok = lexer(ast->value); - if (tok != 'v') - error(); - tok = lexer(str); - while (tok == '+' || tok == '-' || tok == '*' || tok == '/') { + if (tok != 'v') { + //Synopsys-style unquoted identifiers issue#3498 + } else { + //Liberty canonical identifier including double quotes + tok = lexer(str); + } + while (tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') { ast->value += tok; tok = lexer(str); if (tok != 'v') diff --git a/tests/liberty/issue3498_bad.lib b/tests/liberty/issue3498_bad.lib new file mode 100755 index 000000000..f85c4e19b --- /dev/null +++ b/tests/liberty/issue3498_bad.lib @@ -0,0 +1,8 @@ +library(fake) { + cell(bugbad) { + bundle(X) { + members(x1, x2); + power_down_function : !a+b ; + } + } +} From 5a4e72f57a2a9f64e7db9328b68a974986ef7da7 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 8 May 2023 13:13:09 +1200 Subject: [PATCH 12/17] Fix sim writeback check for yw_cosim Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`. This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option. --- passes/sat/sim.cc | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 7c209f516..fe1635249 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1162,6 +1162,11 @@ struct SimWorker : SimShared } for(auto& writer : outputfiles) writer->write(use_signal); + + if (writeback) { + pool wbmods; + top->writeback(wbmods); + } } void update(bool gclk) @@ -1265,11 +1270,6 @@ struct SimWorker : SimShared register_output_step(10*numcycles + 2); write_output_files(); - - if (writeback) { - pool wbmods; - top->writeback(wbmods); - } } void run_cosim_fst(Module *topmod, int numcycles) @@ -1394,11 +1394,6 @@ struct SimWorker : SimShared } write_output_files(); - - if (writeback) { - pool wbmods; - top->writeback(wbmods); - } delete fst; } From 0469405abfe03d5ed31f3bcafb49f708cfa2db45 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 9 May 2023 00:15:34 +0000 Subject: [PATCH 13/17] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 4de857621..55d6af8f3 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.28+12 +YOSYS_VER := 0.28+24 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 9c5a60eb20104f7c320e263631c1371af9576911 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 9 May 2023 07:57:55 +0200 Subject: [PATCH 14/17] Release version 0.29 --- CHANGELOG | 12 +++++++++++- Makefile | 4 ++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 1a74acd9d..bbaad12d6 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,18 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.28 .. Yosys 0.28-dev +Yosys 0.28 .. Yosys 0.29 -------------------------- + * New commands and options + - Added "synthprop" pass for synthesizable properties. + + * Verific support + - Handle conditions on clocked concurrent assertions in unclocked + procedural contexts. + + * Verilog + - Fix const eval of unbased unsized constants. + - Handling of attributes for struct / union variables. Yosys 0.27 .. Yosys 0.28 -------------------------- diff --git a/Makefile b/Makefile index 55d6af8f3..8d5a90344 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.28+24 +YOSYS_VER := 0.29 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -157,7 +157,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 0d6f4b0.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 0d6f4b0.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # From f790e004787706b59bebf1463bdcbb278938d77e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 9 May 2023 08:00:06 +0200 Subject: [PATCH 15/17] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index bbaad12d6..1430f8e2f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.29 .. Yosys 0.29-dev +-------------------------- + Yosys 0.28 .. Yosys 0.29 -------------------------- * New commands and options diff --git a/Makefile b/Makefile index 8d5a90344..2562a233c 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.29 +YOSYS_VER := 0.29+0 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -157,7 +157,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 0d6f4b0.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9c5a60e.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # From c855502bd5bf7d006f2758679a0f2491f90b6f90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Muthiah=20Annamalai=20=28=E0=AE=AE=E0=AF=81=E0=AE=A4?= =?UTF-8?q?=E0=AF=8D=E0=AE=A4=E0=AF=81=20=E0=AE=85=E0=AE=A3=E0=AF=8D?= =?UTF-8?q?=E0=AE=A3=E0=AE=BE=E0=AE=AE=E0=AE=B2=E0=AF=88=29?= Date: Tue, 9 May 2023 06:40:21 -0700 Subject: [PATCH 16/17] Update passes/techmap/libparse.cc Allow Liberty canonical identifier including double quotes in if-body and pass-through for Synopsys-style unquoted identifiers issue#3498 Co-authored-by: Aki <201479+lethalbit@users.noreply.github.com> --- passes/techmap/libparse.cc | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index 1a1726f94..664e99e24 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -236,12 +236,9 @@ LibertyAst *LibertyParser::parse() if (tok == ':' && ast->value.empty()) { tok = lexer(ast->value); - if (tok != 'v') { - //Synopsys-style unquoted identifiers issue#3498 - } else { - //Liberty canonical identifier including double quotes - tok = lexer(str); - } + if (tok == 'v') { + tok = lexer(str); + } while (tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') { ast->value += tok; tok = lexer(str); From d82bae32bee63d4a521e5cb081359aa5a35213f1 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 10 May 2023 00:15:03 +0000 Subject: [PATCH 17/17] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 2562a233c..c622d3bd7 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.29+0 +YOSYS_VER := 0.29+11 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo