mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-24 21:27:00 +00:00
Merge branch 'master' into xc7dsp
This commit is contained in:
David Shah
commit
6919c0f9b0
190 changed files with 8815 additions and 4357 deletions
|
|
@ -29,24 +29,35 @@ module GND(output G);
|
|||
assign G = 0;
|
||||
endmodule
|
||||
|
||||
module IBUF(output O, input I);
|
||||
module IBUF(
|
||||
output O,
|
||||
(* iopad_external_pin *)
|
||||
input I);
|
||||
parameter IOSTANDARD = "default";
|
||||
parameter IBUF_LOW_PWR = 0;
|
||||
assign O = I;
|
||||
endmodule
|
||||
|
||||
module OBUF(output O, input I);
|
||||
module OBUF(
|
||||
(* iopad_external_pin *)
|
||||
output O,
|
||||
input I);
|
||||
parameter IOSTANDARD = "default";
|
||||
parameter DRIVE = 12;
|
||||
parameter SLEW = "SLOW";
|
||||
assign O = I;
|
||||
endmodule
|
||||
|
||||
module BUFG(output O, input I);
|
||||
module BUFG(
|
||||
(* clkbuf_driver *)
|
||||
output O,
|
||||
input I);
|
||||
|
||||
assign O = I;
|
||||
endmodule
|
||||
|
||||
module BUFGCTRL(
|
||||
(* clkbuf_driver *)
|
||||
output O,
|
||||
input I0, input I1,
|
||||
input S0, input S1,
|
||||
|
|
@ -72,7 +83,11 @@ assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
|
|||
|
||||
endmodule
|
||||
|
||||
module BUFHCE(output O, input I, input CE);
|
||||
module BUFHCE(
|
||||
(* clkbuf_driver *)
|
||||
output O,
|
||||
input I,
|
||||
input CE);
|
||||
|
||||
parameter [0:0] INIT_OUT = 1'b0;
|
||||
parameter CE_TYPE = "SYNC";
|
||||
|
|
@ -181,8 +196,16 @@ module XORCY(output O, input CI, LI);
|
|||
assign O = CI ^ LI;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
|
||||
module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
|
||||
(* abc_box_id = 4, lib_whitebox *)
|
||||
module CARRY4(
|
||||
(* abc_carry *)
|
||||
output [3:0] CO,
|
||||
output [3:0] O,
|
||||
(* abc_carry *)
|
||||
input CI,
|
||||
input CYINIT,
|
||||
input [3:0] DI, S
|
||||
);
|
||||
assign O = S ^ {CO[2:0], CI | CYINIT};
|
||||
assign CO[0] = S[0] ? CI | CYINIT : DI[0];
|
||||
assign CO[1] = S[1] ? CO[0] : DI[1];
|
||||
|
|
@ -213,7 +236,7 @@ endmodule
|
|||
|
||||
`endif
|
||||
|
||||
module FDRE (output reg Q, input C, CE, D, R);
|
||||
module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
|
|
@ -225,7 +248,7 @@ module FDRE (output reg Q, input C, CE, D, R);
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
module FDSE (output reg Q, input C, CE, D, S);
|
||||
module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
|
|
@ -237,7 +260,7 @@ module FDSE (output reg Q, input C, CE, D, S);
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
module FDCE (output reg Q, input C, CE, D, CLR);
|
||||
module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
|
|
@ -251,7 +274,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
module FDPE (output reg Q, input C, CE, D, PRE);
|
||||
module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
|
|
@ -265,34 +288,39 @@ module FDPE (output reg Q, input C, CE, D, PRE);
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
module FDRE_1 (output reg Q, input C, CE, D, R);
|
||||
module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module FDSE_1 (output reg Q, input C, CE, D, S);
|
||||
module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module FDCE_1 (output reg Q, input C, CE, D, CLR);
|
||||
module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module FDPE_1 (output reg Q, input C, CE, D, PRE);
|
||||
module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 5, abc_scc_break="D,WE" *)
|
||||
(* abc_box_id = 5 *)
|
||||
module RAM32X1D (
|
||||
output DPO, SPO,
|
||||
input D, WCLK, WE,
|
||||
(* abc_scc_break *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
input WCLK,
|
||||
(* abc_scc_break *)
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
|
||||
);
|
||||
|
|
@ -307,10 +335,15 @@ module RAM32X1D (
|
|||
always @(posedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 6, abc_scc_break="D,WE" *)
|
||||
(* abc_box_id = 6 *)
|
||||
module RAM64X1D (
|
||||
output DPO, SPO,
|
||||
input D, WCLK, WE,
|
||||
(* abc_scc_break *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
input WCLK,
|
||||
(* abc_scc_break *)
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
|
|
@ -325,10 +358,15 @@ module RAM64X1D (
|
|||
always @(posedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 7, abc_scc_break="D,WE" *)
|
||||
(* abc_box_id = 7 *)
|
||||
module RAM128X1D (
|
||||
output DPO, SPO,
|
||||
input D, WCLK, WE,
|
||||
(* abc_scc_break *)
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
input WCLK,
|
||||
(* abc_scc_break *)
|
||||
input WE,
|
||||
input [6:0] A, DPRA
|
||||
);
|
||||
parameter INIT = 128'h0;
|
||||
|
|
@ -342,7 +380,10 @@ endmodule
|
|||
|
||||
module SRL16E (
|
||||
output Q,
|
||||
input A0, A1, A2, A3, CE, CLK, D
|
||||
input A0, A1, A2, A3, CE,
|
||||
(* clkbuf_sink *)
|
||||
input CLK,
|
||||
input D
|
||||
);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
|
@ -354,7 +395,30 @@ module SRL16E (
|
|||
always @(negedge CLK) if (CE) r <= { r[14:0], D };
|
||||
end
|
||||
else
|
||||
always @(posedge CLK) if (CE) r <= { r[14:0], D };
|
||||
always @(posedge CLK) if (CE) r <= { r[14:0], D };
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module SRLC16E (
|
||||
output Q,
|
||||
output Q15,
|
||||
input A0, A1, A2, A3, CE,
|
||||
(* clkbuf_sink *)
|
||||
input CLK,
|
||||
input D
|
||||
);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
||||
reg [15:0] r = INIT;
|
||||
assign Q15 = r[15];
|
||||
assign Q = r[{A3,A2,A1,A0}];
|
||||
generate
|
||||
if (IS_CLK_INVERTED) begin
|
||||
always @(negedge CLK) if (CE) r <= { r[14:0], D };
|
||||
end
|
||||
else
|
||||
always @(posedge CLK) if (CE) r <= { r[14:0], D };
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
|
|
@ -362,7 +426,10 @@ module SRLC32E (
|
|||
output Q,
|
||||
output Q31,
|
||||
input [4:0] A,
|
||||
input CE, CLK, D
|
||||
input CE,
|
||||
(* clkbuf_sink *)
|
||||
input CLK,
|
||||
input D
|
||||
);
|
||||
parameter [31:0] INIT = 32'h00000000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
|
@ -413,7 +480,7 @@ module DSP48E1 (
|
|||
input CEINMODE,
|
||||
input CEM,
|
||||
input CEP,
|
||||
input CLK,
|
||||
(* clkbuf_sink *) input CLK,
|
||||
input [24:0] D,
|
||||
input [4:0] INMODE,
|
||||
input MULTSIGNIN,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue