mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-10 09:15:49 +00:00
Code Activity

remove invalid tests

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-05-07 17:52:31 +02:00
parent 420d65dd9d
commit 68c11321c0
1 changed files with 51 additions and 51 deletions
Download patch file Download diff file Expand all files Collapse all files

104
tests/simple_abc9/abc9.v
View file

@ -47,63 +47,63 @@ module abc9_test008_sub(input a, output b);
assign b = ~a; assign b = ~a;
endmodule endmodule
module abc9_test009(inout io, input oe); // module abc9_test009(inout io, input oe);
reg latch; // reg latch;
always @(io or oe) // always @(io or oe)
if (!oe)
latch <= io;
assign io = oe ? ~latch : 1'bz;
endmodule
module abc9_test010(inout [7:0] io, input oe);
reg [7:0] latch;
always @(io or oe)
if (!oe)
latch <= io;
assign io = oe ? ~latch : 8'bz;
endmodule
module abc9_test011(inout io, input oe);
reg latch;
always @(io or oe)
if (!oe)
latch <= io;
//assign io = oe ? ~latch : 8'bz;
endmodule
module abc9_test012(inout io, input oe);
reg latch;
//always @(io or oe)
// if (!oe) // if (!oe)
// latch <= io; // latch <= io;
assign io = oe ? ~latch : 8'bz; // assign io = oe ? ~latch : 1'bz;
endmodule // endmodule
module abc9_test013(inout [3:0] io, input oe); // module abc9_test010(inout [7:0] io, input oe);
reg [3:0] latch; // reg [7:0] latch;
always @(io or oe) // always @(io or oe)
if (!oe) // if (!oe)
latch[3:0] <= io[3:0]; // latch <= io;
else // assign io = oe ? ~latch : 8'bz;
latch[7:4] <= io; // endmodule
assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
endmodule
module abc9_test014(inout [7:0] io, input oe); // module abc9_test011(inout io, input oe);
abc9_test012_sub sub(io, oe); // reg latch;
endmodule // always @(io or oe)
// if (!oe)
// latch <= io;
// //assign io = oe ? ~latch : 8'bz;
// endmodule
module abc9_test012_sub(inout [7:0] io, input oe); // module abc9_test012(inout io, input oe);
reg [7:0] latch; // reg latch;
always @(io or oe) // //always @(io or oe)
if (!oe) // // if (!oe)
latch[3:0] <= io; // // latch <= io;
else // assign io = oe ? ~latch : 8'bz;
latch[7:4] <= io; // endmodule
assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; // // module abc9_test013(inout [3:0] io, input oe);
endmodule // // reg [7:0] latch;
// // always @(io or oe)
// // if (!oe)
// // latch[3:0] <= io[3:0];
// // else
// // latch[7:4] <= io;
// // assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
// // assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
// // endmodule
// module abc9_test014(inout [7:0] io, input oe);
// abc9_test012_sub sub(io, oe);
// endmodule
// module abc9_test012_sub(inout [7:0] io, input oe);
// reg [7:0] latch;
// always @(io or oe)
// if (!oe)
// latch[3:0] <= io;
// else
// latch[7:4] <= io;
// assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
// assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
// endmodule
module abc9_test015(input a, output b, input c); module abc9_test015(input a, output b, input c);
assign b = ~a; assign b = ~a;