Merge af7d1d3f4f into 012ddc2f1e

passes/sat/cutpoint.cc

@@ -109,13 +109,43 @@ struct CutpointPass : public Pass {
 			SigMap sigmap(module);
 			pool<SigBit> cutpoint_bits;
 
+			pool<SigBit> wire_drivers;
+			for (auto cell : module->cells())
+				for (auto &conn : cell->connections())
+					if (cell->output(conn.first) && !cell->input(conn.first))
+						for (auto bit : sigmap(conn.second))
+							if (bit.wire)
+								wire_drivers.insert(bit);
+			
+			for (auto wire : module->wires())
+				if (wire->port_input)
+					for (auto bit : sigmap(wire))
+						wire_drivers.insert(bit);
+
 			for (auto cell : module->selected_cells()) {
 				if (cell->type == ID($anyseq))
 					continue;
 				log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
 				for (auto &conn : cell->connections()) {
-					if (cell->output(conn.first))
+					if (cell->output(conn.first)) {
+						bool do_cut = true;
+						if (cell->input(conn.first))
+							for (auto bit : sigmap(conn.second))
+								if (wire_drivers.count(bit)) {
+									log_debug("  Treating inout port '%s' as input.\n", id2cstr(conn.first));
+									do_cut = false;
+									break;
+								}
+
+						if (do_cut) {
 							module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second)));
+							if (cell->input(conn.first)) {
+								log_debug("  Treating inout port '%s' as output.\n", id2cstr(conn.first));
+								for (auto bit : sigmap(conn.second))
+									wire_drivers.insert(bit);
+							}
+						}
+					}
 				}
 
 				RTLIL::Cell *scopeinfo = nullptr;

tests/various/cutpoint_blackbox.ys

@@ -70,3 +70,44 @@ design -load gold
 select -read cutpoint.gate.sel
 # nothing in gold but not gate
 select -assert-none % %n
+
+# replacing the blackbox with a verific-style unknown module should work too
+# (note this specific example loses the values of SOME_PARAM which would
+#  normally be retained by verific)
+design -load hier
+delete =bb
+read_rtlil << EOT
+attribute \blackbox 1
+module \bb
+    parameter \SOME_PARAM 0
+    wire inout 3 \o
+    wire inout 2 \b
+    wire inout 1 \a
+end
+EOT
+cutpoint -blackbox
+check -assert
+
+# also concatenated signals, and signals between two inout ports
+design -load hier
+delete top =bb
+read_verilog << EOT
+module top(input [1:0] a, b, output [1:0] o);
+    wire [1:0] c, d, e;
+    bb #(.SOME_PARAM(1)) bb1 (.a ({a[0], e[1]}), .b (b), .o (c));
+    bb #(.SOME_PARAM(2)) bb2 (.a ({c[1], a[0]}), .b (c), .o (d));
+    wb wb1 (.a (a), .b (b), .o (e));
+    some_mod some_inst (.a (c), .b (d), .c (e), .o (o));
+endmodule
+EOT
+read_rtlil << EOT
+attribute \blackbox 1
+module \bb
+    parameter \SOME_PARAM 0
+    wire inout 3 width 2 \o
+    wire inout 2 width 2 \b
+    wire inout 1 width 2 \a
+end
+EOT
+cutpoint -blackbox
+check -assert