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Merge af7d1d3f4f into 012ddc2f1e

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KrystalDelusion 2025-09-08 10:10:29 +12:00 • committed by GitHub
commit 67b4e5be87
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2 changed files with 73 additions and 2 deletions
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34
passes/sat/cutpoint.cc
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@ -109,13 +109,43 @@ struct CutpointPass : public Pass {
SigMap sigmap(module);
pool<SigBit> cutpoint_bits;
pool<SigBit> wire_drivers;
for (auto cell : module->cells())
for (auto &conn : cell->connections())
if (cell->output(conn.first) && !cell->input(conn.first))
for (auto bit : sigmap(conn.second))
if (bit.wire)
wire_drivers.insert(bit);
for (auto wire : module->wires())
if (wire->port_input)
for (auto bit : sigmap(wire))
wire_drivers.insert(bit);
for (auto cell : module->selected_cells()) {
if (cell->type == ID($anyseq))
continue;
log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
for (auto &conn : cell->connections()) {
if (cell->output(conn.first))
module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second)));
if (cell->output(conn.first)) {
bool do_cut = true;
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
if (wire_drivers.count(bit)) {
log_debug(" Treating inout port '%s' as input.\n", id2cstr(conn.first));
do_cut = false;
break;
}
if (do_cut) {
module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second)));
if (cell->input(conn.first)) {
log_debug(" Treating inout port '%s' as output.\n", id2cstr(conn.first));
for (auto bit : sigmap(conn.second))
wire_drivers.insert(bit);
}
}
}
}
RTLIL::Cell *scopeinfo = nullptr;