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rtlil: add source tracking to CaseRule actions

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(cherry picked from commit c36370f227)
This commit is contained in:
Emil J. Tywoniak 2025-11-02 11:25:42 +01:00
parent 292d44f208
commit 6646b1dbf9
7 changed files with 18 additions and 17 deletions
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4
backends/rtlil/rtlil_backend.cc
View file

@ -259,7 +259,7 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::
void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs, const RTLIL::Design *design, DumpMode mode) void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs, const RTLIL::Design *design, DumpMode mode)
{ {
for (const auto& [lhs, rhs] : cs->actions) { for (const auto& [lhs, rhs, _] : cs->actions) {
f << stringf("%s" "assign ", indent); f << stringf("%s" "assign ", indent);
dump_sigspec(f, lhs, true, mode); dump_sigspec(f, lhs, true, mode);
f << stringf(" "); f << stringf(" ");
@ -313,7 +313,7 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT
case RTLIL::STi: f << stringf("init\n"); break; case RTLIL::STi: f << stringf("init\n"); break;
} }
for (const auto& [lhs, rhs] : sy->actions) { for (const auto& [lhs, rhs, _] : sy->actions) {
f << stringf("%s update ", indent); f << stringf("%s update ", indent);
dump_sigspec(f, lhs, true, mode); dump_sigspec(f, lhs, true, mode);
f << stringf(" "); f << stringf(" ");

14
frontends/ast/genrtlil.cc
View file

@ -464,7 +464,7 @@ struct AST_INTERNAL::ProcessGenerator
RTLIL::SigSpec lhs = init_lvalue_c; RTLIL::SigSpec lhs = init_lvalue_c;
RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width); RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
remove_unwanted_lvalue_bits(lhs, rhs); remove_unwanted_lvalue_bits(lhs, rhs);
sync->actions.push_back({lhs, rhs}); sync->actions.push_back({lhs, rhs, Twine::Null});
offset += lhs.size(); offset += lhs.size();
} }
} }
@ -624,7 +624,7 @@ struct AST_INTERNAL::ProcessGenerator
if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync)) if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync))
rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size()); rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
remove_unwanted_lvalue_bits(lhs, rhs); remove_unwanted_lvalue_bits(lhs, rhs);
actions.push_back({lhs, rhs}); actions.push_back({lhs, rhs, ast ? current_module->design->twines.add(std::string{ast->loc_string()}) : Twine::Null});
offset += lhs.size(); offset += lhs.size();
} }
} }
@ -680,7 +680,7 @@ struct AST_INTERNAL::ProcessGenerator
current_case_assigned_bits.insert(bit); current_case_assigned_bits.insert(bit);
remove_unwanted_lvalue_bits(lvalue, rvalue); remove_unwanted_lvalue_bits(lvalue, rvalue);
current_case->actions.push_back({lvalue, rvalue}); current_case->actions.push_back({lvalue, rvalue, current_module->design->twines.add(std::string{ast->loc_string()})});
} }
break; break;
@ -823,8 +823,8 @@ struct AST_INTERNAL::ProcessGenerator
Wire *en = current_module->addWire(current_module->design->twines.add(std::string{sstr.str() + "_EN"}), 1); Wire *en = current_module->addWire(current_module->design->twines.add(std::string{sstr.str() + "_EN"}), 1);
set_src_attr(en, ast); set_src_attr(en, ast);
proc->root_case.actions.push_back({en, SigSpec(false)}); proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(std::string{ast->loc_string()})});
current_case->actions.push_back({en, SigSpec(true)}); current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(std::string{ast->loc_string()})});
RTLIL::SigSpec triggers; RTLIL::SigSpec triggers;
RTLIL::Const::Builder polarity_builder; RTLIL::Const::Builder polarity_builder;
@ -921,8 +921,8 @@ struct AST_INTERNAL::ProcessGenerator
Wire *en = current_module->addWire(current_module->design->twines.add(std::string{cellname.str() + "_EN"}), 1); Wire *en = current_module->addWire(current_module->design->twines.add(std::string{cellname.str() + "_EN"}), 1);
set_src_attr(en, ast); set_src_attr(en, ast);
proc->root_case.actions.push_back({en, SigSpec(false)}); proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(std::string{ast->loc_string()})});
current_case->actions.push_back({en, SigSpec(true)}); current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(std::string{ast->loc_string()})});
RTLIL::SigSpec triggers; RTLIL::SigSpec triggers;
RTLIL::Const::Builder polarity_builder; RTLIL::Const::Builder polarity_builder;

4
frontends/rtlil/rtlil_frontend.cc
View file

@ -926,7 +926,7 @@ struct RTLILFrontendWorker {
"The assign statement is reordered to come before all switch statements."); "The assign statement is reordered to come before all switch statements.");
RTLIL::SigSpec s1 = parse_sigspec(); RTLIL::SigSpec s1 = parse_sigspec();
RTLIL::SigSpec s2 = parse_sigspec(); RTLIL::SigSpec s2 = parse_sigspec();
current_case->actions.push_back({std::move(s1), std::move(s2)}); current_case->actions.push_back({std::move(s1), std::move(s2), Twine::Null});
expect_eol(); expect_eol();
} else } else
return; return;
@ -1027,7 +1027,7 @@ struct RTLILFrontendWorker {
if (try_parse_keyword("update")) { if (try_parse_keyword("update")) {
RTLIL::SigSpec s1 = parse_sigspec(); RTLIL::SigSpec s1 = parse_sigspec();
RTLIL::SigSpec s2 = parse_sigspec(); RTLIL::SigSpec s2 = parse_sigspec();
rule->actions.push_back({std::move(s1), std::move(s2)}); rule->actions.push_back({std::move(s1), std::move(s2), Twine::Null});
expect_eol(); expect_eol();
continue; continue;
} }

1
kernel/rtlil.h
View file

@ -2603,6 +2603,7 @@ struct RTLIL::SyncAction
{ {
RTLIL::SigSpec lhs; RTLIL::SigSpec lhs;
RTLIL::SigSpec rhs; RTLIL::SigSpec rhs;
TwineRef src = Twine::Null;
}; };
struct RTLIL::SyncRule struct RTLIL::SyncRule

2
passes/proc/proc_arst.cc
View file

@ -315,7 +315,7 @@ struct ProcArstPass : public Pass {
if (arst_sig.size()) { if (arst_sig.size()) {
log("Added global reset to process %s: %s <- %s\n", log("Added global reset to process %s: %s <- %s\n",
log_id(proc), log_signal(arst_sig), log_signal(arst_val)); log_id(proc), log_signal(arst_sig), log_signal(arst_val));
arst_actions.push_back({arst_sig, arst_val}); arst_actions.push_back({arst_sig, arst_val, act.src});
} }
} }
if (!arst_actions.empty()) { if (!arst_actions.empty()) {

2
passes/proc/proc_dff.cc
View file

@ -223,7 +223,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
// as ones coming from the module // as ones coming from the module
single_async_rule.type = RTLIL::SyncType::ST1; single_async_rule.type = RTLIL::SyncType::ST1;
single_async_rule.signal = mod->ReduceOr(NEW_TWINE, triggers); single_async_rule.signal = mod->ReduceOr(NEW_TWINE, triggers);
single_async_rule.actions.push_back({sig, rstval}); single_async_rule.actions.push_back({sig, rstval, Twine::Null});
// Replace existing rules with this new rule // Replace existing rules with this new rule
async_rules.clear(); async_rules.clear();

8
passes/proc/proc_rom.cc
View file

@ -193,23 +193,23 @@ struct RomWorker
delete cs; delete cs;
sw->cases.clear(); sw->cases.clear();
sw->signal = sw->signal.extract(0, swsigbits); sw->signal = sw->signal.extract(0, swsigbits);
Const action_src = mem.has_attribute(ID::src) ? mem.attributes[ID::src] : Const(""); TwineRef action_src = sw->src_id();
if (abits == GetSize(sw->signal)) { if (abits == GetSize(sw->signal)) {
sw->signal = SigSpec(); sw->signal = SigSpec();
RTLIL::CaseRule *cs = new RTLIL::CaseRule; RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->module = module; cs->module = module;
cs->actions.push_back({lhs, rdata}); cs->actions.push_back({lhs, rdata, action_src});
sw->cases.push_back(cs); sw->cases.push_back(cs);
} else { } else {
sw->signal = sw->signal.extract_end(abits); sw->signal = sw->signal.extract_end(abits);
RTLIL::CaseRule *cs = new RTLIL::CaseRule; RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->module = module; cs->module = module;
cs->compare.push_back(Const(State::S0, GetSize(sw->signal))); cs->compare.push_back(Const(State::S0, GetSize(sw->signal)));
cs->actions.push_back({lhs, rdata}); cs->actions.push_back({lhs, rdata, action_src});
sw->cases.push_back(cs); sw->cases.push_back(cs);
RTLIL::CaseRule *cs2 = new RTLIL::CaseRule; RTLIL::CaseRule *cs2 = new RTLIL::CaseRule;
cs2->module = module; cs2->module = module;
cs2->actions.push_back({lhs, default_val}); cs2->actions.push_back({lhs, default_val, action_src});
sw->cases.push_back(cs2); sw->cases.push_back(cs2);
} }