diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc
index 8d20ea55c..ae2a95fd2 100644
--- a/backends/rtlil/rtlil_backend.cc
+++ b/backends/rtlil/rtlil_backend.cc
@@ -259,7 +259,7 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::
 
 void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs, const RTLIL::Design *design, DumpMode mode)
 {
-	for (const auto& [lhs, rhs] : cs->actions) {
+	for (const auto& [lhs, rhs, _] : cs->actions) {
 		f << stringf("%s" "assign ", indent);
 		dump_sigspec(f, lhs, true, mode);
 		f << stringf(" ");
@@ -313,7 +313,7 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT
 	case RTLIL::STi: f << stringf("init\n"); break;
 	}
 
-	for (const auto& [lhs, rhs] : sy->actions) {
+	for (const auto& [lhs, rhs, _] : sy->actions) {
 		f << stringf("%s  update ", indent);
 		dump_sigspec(f, lhs, true, mode);
 		f << stringf(" ");
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 45ced58af..cfbe6e396 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -464,7 +464,7 @@ struct AST_INTERNAL::ProcessGenerator
 				RTLIL::SigSpec lhs = init_lvalue_c;
 				RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
 				remove_unwanted_lvalue_bits(lhs, rhs);
-				sync->actions.push_back({lhs, rhs});
+				sync->actions.push_back({lhs, rhs, Twine::Null});
 				offset += lhs.size();
 			}
 		}
@@ -624,7 +624,7 @@ struct AST_INTERNAL::ProcessGenerator
 			if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync))
 				rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
 			remove_unwanted_lvalue_bits(lhs, rhs);
-			actions.push_back({lhs, rhs});
+			actions.push_back({lhs, rhs, ast ? current_module->design->twines.add(std::string{ast->loc_string()}) : Twine::Null});
 			offset += lhs.size();
 		}
 	}
@@ -680,7 +680,7 @@ struct AST_INTERNAL::ProcessGenerator
 						current_case_assigned_bits.insert(bit);
 
 				remove_unwanted_lvalue_bits(lvalue, rvalue);
-				current_case->actions.push_back({lvalue, rvalue});
+				current_case->actions.push_back({lvalue, rvalue, current_module->design->twines.add(std::string{ast->loc_string()})});
 			}
 			break;
 
@@ -823,8 +823,8 @@ struct AST_INTERNAL::ProcessGenerator
 
 				Wire *en = current_module->addWire(current_module->design->twines.add(std::string{sstr.str() + "_EN"}), 1);
 				set_src_attr(en, ast);
-				proc->root_case.actions.push_back({en, SigSpec(false)});
-				current_case->actions.push_back({en, SigSpec(true)});
+				proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(std::string{ast->loc_string()})});
+				current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(std::string{ast->loc_string()})});
 
 				RTLIL::SigSpec triggers;
 				RTLIL::Const::Builder polarity_builder;
@@ -921,8 +921,8 @@ struct AST_INTERNAL::ProcessGenerator
 
 				Wire *en = current_module->addWire(current_module->design->twines.add(std::string{cellname.str() + "_EN"}), 1);
 				set_src_attr(en, ast);
-				proc->root_case.actions.push_back({en, SigSpec(false)});
-				current_case->actions.push_back({en, SigSpec(true)});
+				proc->root_case.actions.push_back({en, SigSpec(false), current_module->design->twines.add(std::string{ast->loc_string()})});
+				current_case->actions.push_back({en, SigSpec(true), current_module->design->twines.add(std::string{ast->loc_string()})});
 
 				RTLIL::SigSpec triggers;
 				RTLIL::Const::Builder polarity_builder;
diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc
index dbd1635dc..4a1192770 100644
--- a/frontends/rtlil/rtlil_frontend.cc
+++ b/frontends/rtlil/rtlil_frontend.cc
@@ -926,7 +926,7 @@ struct RTLILFrontendWorker {
 						"The assign statement is reordered to come before all switch statements.");
 				RTLIL::SigSpec s1 = parse_sigspec();
 				RTLIL::SigSpec s2 = parse_sigspec();
-				current_case->actions.push_back({std::move(s1), std::move(s2)});
+				current_case->actions.push_back({std::move(s1), std::move(s2), Twine::Null});
 				expect_eol();
 			} else
 				return;
@@ -1027,7 +1027,7 @@ struct RTLILFrontendWorker {
 				if (try_parse_keyword("update")) {
 					RTLIL::SigSpec s1 = parse_sigspec();
 					RTLIL::SigSpec s2 = parse_sigspec();
-					rule->actions.push_back({std::move(s1), std::move(s2)});
+					rule->actions.push_back({std::move(s1), std::move(s2), Twine::Null});
 					expect_eol();
 					continue;
 				}
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index c63733979..bbcf58417 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -2603,6 +2603,7 @@ struct RTLIL::SyncAction
 {
 	RTLIL::SigSpec lhs;
 	RTLIL::SigSpec rhs;
+	TwineRef src = Twine::Null;
 };
 
 struct RTLIL::SyncRule
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index e2ec532c0..05b52eace 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -315,7 +315,7 @@ struct ProcArstPass : public Pass {
 							if (arst_sig.size()) {
 								log("Added global reset to process %s: %s <- %s\n",
 										log_id(proc), log_signal(arst_sig), log_signal(arst_val));
-								arst_actions.push_back({arst_sig, arst_val});
+								arst_actions.push_back({arst_sig, arst_val, act.src});
 							}
 						}
 				if (!arst_actions.empty()) {
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index d3fbf849f..d20567e18 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -223,7 +223,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 			// as ones coming from the module
 			single_async_rule.type = RTLIL::SyncType::ST1;
 			single_async_rule.signal = mod->ReduceOr(NEW_TWINE, triggers);
-			single_async_rule.actions.push_back({sig, rstval});
+			single_async_rule.actions.push_back({sig, rstval, Twine::Null});
 
 			// Replace existing rules with this new rule
 			async_rules.clear();
diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc
index 8997b35fc..d51d28c27 100644
--- a/passes/proc/proc_rom.cc
+++ b/passes/proc/proc_rom.cc
@@ -193,23 +193,23 @@ struct RomWorker
 			delete cs;
 		sw->cases.clear();
 		sw->signal = sw->signal.extract(0, swsigbits);
-		Const action_src = mem.has_attribute(ID::src) ? mem.attributes[ID::src] : Const("");
+		TwineRef action_src = sw->src_id();
 		if (abits == GetSize(sw->signal)) {
 			sw->signal = SigSpec();
 			RTLIL::CaseRule *cs = new RTLIL::CaseRule;
 			cs->module = module;
-			cs->actions.push_back({lhs, rdata});
+			cs->actions.push_back({lhs, rdata, action_src});
 			sw->cases.push_back(cs);
 		} else {
 			sw->signal = sw->signal.extract_end(abits);
 			RTLIL::CaseRule *cs = new RTLIL::CaseRule;
 			cs->module = module;
 			cs->compare.push_back(Const(State::S0, GetSize(sw->signal)));
-			cs->actions.push_back({lhs, rdata});
+			cs->actions.push_back({lhs, rdata, action_src});
 			sw->cases.push_back(cs);
 			RTLIL::CaseRule *cs2 = new RTLIL::CaseRule;
 			cs2->module = module;
-			cs2->actions.push_back({lhs, default_val});
+			cs2->actions.push_back({lhs, default_val, action_src});
 			sw->cases.push_back(cs2);
 		}