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rtlil: add source tracking to CaseRule actions

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(cherry picked from commit c36370f227)
This commit is contained in:
Emil J. Tywoniak 2025-11-02 11:25:42 +01:00
parent 292d44f208
commit 6646b1dbf9
7 changed files with 18 additions and 17 deletions
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2
passes/proc/proc_arst.cc
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@ -315,7 +315,7 @@ struct ProcArstPass : public Pass {
if (arst_sig.size()) {
log("Added global reset to process %s: %s <- %s\n",
log_id(proc), log_signal(arst_sig), log_signal(arst_val));
arst_actions.push_back({arst_sig, arst_val});
arst_actions.push_back({arst_sig, arst_val, act.src});
}
}
if (!arst_actions.empty()) {

2
passes/proc/proc_dff.cc
View file

@ -223,7 +223,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
// as ones coming from the module
single_async_rule.type = RTLIL::SyncType::ST1;
single_async_rule.signal = mod->ReduceOr(NEW_TWINE, triggers);
single_async_rule.actions.push_back({sig, rstval});
single_async_rule.actions.push_back({sig, rstval, Twine::Null});
// Replace existing rules with this new rule
async_rules.clear();

8
passes/proc/proc_rom.cc
View file

@ -193,23 +193,23 @@ struct RomWorker
delete cs;
sw->cases.clear();
sw->signal = sw->signal.extract(0, swsigbits);
Const action_src = mem.has_attribute(ID::src) ? mem.attributes[ID::src] : Const("");
TwineRef action_src = sw->src_id();
if (abits == GetSize(sw->signal)) {
sw->signal = SigSpec();
RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->module = module;
cs->actions.push_back({lhs, rdata});
cs->actions.push_back({lhs, rdata, action_src});
sw->cases.push_back(cs);
} else {
sw->signal = sw->signal.extract_end(abits);
RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->module = module;
cs->compare.push_back(Const(State::S0, GetSize(sw->signal)));
cs->actions.push_back({lhs, rdata});
cs->actions.push_back({lhs, rdata, action_src});
sw->cases.push_back(cs);
RTLIL::CaseRule *cs2 = new RTLIL::CaseRule;
cs2->module = module;
cs2->actions.push_back({lhs, default_val});
cs2->actions.push_back({lhs, default_val, action_src});
sw->cases.push_back(cs2);
}