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This commit is contained in:
Emil J. Tywoniak 2024-06-14 17:26:48 +02:00
parent eeb15ea2a2
commit 65d50db4ef
13 changed files with 74 additions and 67 deletions
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2
passes/opt/opt_expr.cc
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@ -409,7 +409,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') {
if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
GetSize(cell->getPort(ID::B)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
if (cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))

4
passes/techmap/extractinv.cc
View file

@ -102,9 +102,9 @@ struct ExtractinvPass : public Pass {
if (it2 == cell->parameters.end())
continue;
SigSpec sig = port.second;
if (it2->second.size() != sig.size())
if ((*it2).second.size() != sig.size())
log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", log_id(module->name), log_id(cell->type), log_id(port.first), log_id(param_name));
RTLIL::Const invmask = it2->second;
RTLIL::Const invmask = (*it2).second;
cell->parameters.erase(param_name);
if (invmask.is_fully_zero())
continue;

2
passes/tests/test_cell.cc
View file

@ -345,7 +345,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
if (constmode)
{
auto conn_list = cell->connections();
for (auto &conn : conn_list)
for (auto conn : conn_list)
{
RTLIL::SigSpec sig = conn.second;