From 65d50db4efcfef6d5ba93755ee06d5db4f5682d7 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 14 Jun 2024 17:26:48 +0200 Subject: [PATCH] 100% --- Makefile | 4 ++-- backends/blif/blif.cc | 5 +++-- backends/cxxrtl/cxxrtl_backend.cc | 3 ++- backends/firrtl/firrtl.cc | 18 ++++++++-------- backends/jny/jny.cc | 5 +++-- backends/json/json.cc | 6 +++--- backends/verilog/verilog_backend.cc | 24 ++++++++++----------- kernel/register.cc | 3 --- kernel/rtlil.cc | 33 ++++++++++++++++------------- kernel/rtlil.h | 32 ++++++++++++++++------------ passes/opt/opt_expr.cc | 2 +- passes/techmap/extractinv.cc | 4 ++-- passes/tests/test_cell.cc | 2 +- 13 files changed, 74 insertions(+), 67 deletions(-) diff --git a/Makefile b/Makefile index 8547acb11..9db758ef8 100644 --- a/Makefile +++ b/Makefile @@ -45,10 +45,10 @@ DISABLE_SPAWN := 0 DISABLE_ABC_THREADS := 0 # clang sanitizers -SANITIZER = +# SANITIZER = # SANITIZER = address # SANITIZER = memory -# SANITIZER = undefined +SANITIZER = undefined # SANITIZER = cfi PROGRAM_PREFIX := diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 788b7f951..f97af5727 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -141,9 +141,10 @@ struct BlifDumper return "subckt"; } - void dump_params(const char *command, dict ¶ms) + template + void dump_params(const char *command, SmellsLikeDict ¶ms) { - for (auto ¶m : params) { + for (auto param : params) { f << stringf("%s %s ", command, log_id(param.first)); if (param.second.flags & RTLIL::CONST_FLAG_STRING) { std::string str = param.second.decode_string(); diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 9ddbd33b0..1839e215e 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -2326,7 +2326,8 @@ struct CxxrtlWorker { f << escape_c_string(data); } - void dump_metadata_map(const dict &metadata_map) { + template + void dump_metadata_map(const SmellsLikeDict &metadata_map) { if (metadata_map.empty()) { f << "metadata_map()"; } else { diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index dc76dbeec..c4902cb93 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -480,17 +480,17 @@ struct FirrtlWorker wire_exprs.push_back(stringf("%s" "inst %s%s of %s %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), instanceName.c_str(), cellFileinfo.c_str())); for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) { - if (it->second.size() > 0) { - const SigSpec &secondSig = it->second; - const std::string firstName = cell_name + "." + make_id(it->first); + if ((*it).second.size() > 0) { + const SigSpec &secondSig = (*it).second; + const std::string firstName = cell_name + "." + make_id((*it).first); const std::string secondExpr = make_expr(secondSig); // Find the direction for this port. - FDirection dir = getPortFDirection(it->first, instModule); + FDirection dir = getPortFDirection((*it).first, instModule); std::string sourceExpr, sinkExpr; const SigSpec *sinkSig = nullptr; switch (dir) { case FD_INOUT: - log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type.c_str(), log_signal(it->second)); + log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type.c_str(), log_signal((*it).second)); YS_FALLTHROUGH case FD_OUT: sourceExpr = firstName; @@ -498,14 +498,14 @@ struct FirrtlWorker sinkSig = &secondSig; break; case FD_NODIRECTION: - log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type.c_str(), log_signal(it->second)); + log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type.c_str(), log_signal((*it).second)); YS_FALLTHROUGH case FD_IN: sourceExpr = secondExpr; sinkExpr = firstName; break; default: - log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir); + log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal((*it).second), dir); break; } // Check for subfield assignment. @@ -849,7 +849,7 @@ struct FirrtlWorker } auto it = cell->parameters.find(ID::B_SIGNED); - if (it == cell->parameters.end() || !it->second.as_bool()) { + if (it == cell->parameters.end() || !(*it).second.as_bool()) { b_expr = "asUInt(" + b_expr + ")"; } @@ -881,7 +881,7 @@ struct FirrtlWorker if (cell->type.in(ID($mux), ID($_MUX_))) { auto it = cell->parameters.find(ID::WIDTH); - int width = it == cell->parameters.end()? 1 : it->second.as_int(); + int width = it == cell->parameters.end()? 1 : (*it).second.as_int(); string a_expr = make_expr(cell->getPort(ID::A)); string b_expr = make_expr(cell->getPort(ID::B)); string s_expr = make_expr(cell->getPort(ID::S)); diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc index 1c163dba5..5a5be5656 100644 --- a/backends/jny/jny.cc +++ b/backends/jny/jny.cc @@ -342,11 +342,12 @@ struct JnyWriter } } - void write_prams(dict& params, uint16_t indent_level = 0) { + template + void write_prams(SmellsLikeDict& params, uint16_t indent_level = 0) { const auto _indent = gen_indent(indent_level); bool first_param{true}; - for (auto& param : params) { + for (auto param : params) { if (!first_param) f << stringf(",\n"); const auto param_val = param.second; diff --git a/backends/json/json.cc b/backends/json/json.cc index 2f442c494..c3e75fe2a 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -128,11 +128,11 @@ struct JsonWriter f << get_string(value.as_string()); } } - - void write_parameters(const dict ¶meters, bool for_module=false) + template + void write_parameters(const SmellsLikeDict ¶meters, bool for_module=false) { bool first = true; - for (auto ¶m : parameters) { + for (auto param : parameters) { f << stringf("%s\n", first ? "" : ","); f << stringf(" %s%s: ", for_module ? "" : " ", get_name(param.first).c_str()); write_parameter_value(param.second); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 31bbc996f..06862531a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1895,9 +1895,9 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) { if (it != cell->parameters.begin()) f << stringf(","); - f << stringf("\n%s .%s(", indent.c_str(), id(it->first).c_str()); - if (it->second.size() > 0) - dump_const(f, it->second); + f << stringf("\n%s .%s(", indent.c_str(), id((*it).first).c_str()); + if ((*it).second.size() > 0) + dump_const(f, (*it).second); f << stringf(")"); } f << stringf("\n%s" ")", indent.c_str()); @@ -1915,36 +1915,36 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) char str[16]; snprintf(str, 16, "$%d", i); for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) { - if (it->first != str) + if ((*it).first != str) continue; if (!first_arg) f << stringf(","); first_arg = false; f << stringf("\n%s ", indent.c_str()); - dump_sigspec(f, it->second); - numbered_ports.insert(it->first); + dump_sigspec(f, (*it).second); + numbered_ports.insert((*it).first); goto found_numbered_port; } break; found_numbered_port:; } for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) { - if (numbered_ports.count(it->first)) + if (numbered_ports.count((*it).first)) continue; if (!first_arg) f << stringf(","); first_arg = false; - f << stringf("\n%s .%s(", indent.c_str(), id(it->first).c_str()); - if (it->second.size() > 0) - dump_sigspec(f, it->second); + f << stringf("\n%s .%s(", indent.c_str(), id((*it).first).c_str()); + if ((*it).second.size() > 0) + dump_sigspec(f, (*it).second); f << stringf(")"); } f << stringf("\n%s" ");\n", indent.c_str()); if (defparam && cell->parameters.size() > 0) { for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) { - f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str()); - dump_const(f, it->second); + f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id((*it).first).c_str()); + dump_const(f, (*it).second); f << stringf(";\n"); } } diff --git a/kernel/register.cc b/kernel/register.cc index e3f6ede3c..80bc44901 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -314,9 +314,6 @@ void Pass::call(RTLIL::Design *design, std::vector args) size_t orig_sel_stack_pos = design->selection_stack.size(); auto state = pass_register[args[0]]->pre_execute(); - ZoneScopedN(pass_name.c_str()); - // ZoneText(pass_name.c_str(), pass_name.length()); - ZoneColor((uint32_t)(size_t)pass_name.c_str()); pass_register[args[0]]->execute(args, design); pass_register[args[0]]->post_execute(state); while (design->selection_stack.size() > orig_sel_stack_pos) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7d46a5c0a..2aa0c5b1d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2428,26 +2428,29 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) { RTLIL::Cell *cell = new RTLIL::Cell; // std::cout << "alloc " << (long long)cell << " called " << cell->name.c_str() << "\n"; + cell->module = this; cell->name = name; cell->type = type; if (RTLIL::Cell::is_legacy_type(type)) { - auto legOldCell = new RTLIL::OldCell; - legOldCell->name = name; - legOldCell->type = type; + std::cout << "new RTLIL::OldCell\n"; + cell->legacy = new RTLIL::OldCell; + cell->legacy->name = name; + cell->legacy->type = type; } add(cell); return cell; } -// TODO ? brokey -// RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::OldCell *other) -// { -// RTLIL::Cell *cell = addCell(name, other->type); -// cell->connections_ = other->connections_; -// cell->parameters = other->parameters; -// cell->attributes = other->attributes; -// return cell; -// } +RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other) +{ + RTLIL::Cell *cell = addCell(name, other->type); + cell->module = this; + cell->connections_ = other->connections_; + cell->parameters = other->parameters; + cell->attributes = other->attributes; + add(cell); + return cell; +} RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other) { @@ -2493,9 +2496,9 @@ RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Pro add ## _func(name, sig_a, sig_y, is_signed, src); \ return sig_y; \ } -// DEF_METHOD(Not, sig_a.size(), ID($not)) -// DEF_METHOD(Pos, sig_a.size(), ID($pos)) -// DEF_METHOD(Neg, sig_a.size(), ID($neg)) +DEF_METHOD(Not, sig_a.size(), ID($not)) +DEF_METHOD(Pos, sig_a.size(), ID($pos)) +DEF_METHOD(Neg, sig_a.size(), ID($neg)) DEF_METHOD(ReduceAnd, 1, ID($reduce_and)) DEF_METHOD(ReduceOr, 1, ID($reduce_or)) DEF_METHOD(ReduceXor, 1, ID($reduce_xor)) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 47d0e7cb2..0b79b27b1 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1776,13 +1776,13 @@ public: throw std::out_of_range("FakeParams::size()"); } } - bool empty() { + bool empty() const { return !size(); } // The need for this function implies setPort will be used on incompat types - void erase(const RTLIL::IdString& paramname) { (void)paramname; } + void erase(const RTLIL::IdString& paramname) const { (void)paramname; } // The need for this function implies setPort will be used on incompat types - void clear() {} + void clear() const {} // AAA class iterator { typedef std::bidirectional_iterator_tag iterator_category; @@ -1821,8 +1821,8 @@ public: throw std::out_of_range("FakeParams::iterator::operator*()"); } } - // std::pair operator->() { return operator*(); } - // const std::pair operator->() const { return operator*(); } + std::pair operator->() { return operator*(); } + const std::pair operator->() const { return operator*(); } const std::pair operator*() const { if (parent->is_legacy()) { auto it = parent->legacy->parameters.begin(); @@ -1901,6 +1901,8 @@ public: throw std::out_of_range("FakeParams::const_iterator::operator*() const"); } } + std::pair operator->() { return operator*(); } + const std::pair operator->() const { return operator*(); } }; const_iterator begin() const { return const_iterator(parent, 0); @@ -1926,7 +1928,7 @@ public: }; struct FakeConns { RTLIL::Cell* parent; - RTLIL::SigSpec at(RTLIL::IdString name) { + RTLIL::SigSpec& at(RTLIL::IdString name) { return parent->getMutPort(name); } const RTLIL::SigSpec& at(RTLIL::IdString name) const { @@ -2021,8 +2023,8 @@ public: // The need for this function implies setPort will be used on incompat types void erase(const RTLIL::IdString& portname) { (void)portname; } // The need for this function implies setPort will be used on incompat types - void clear() {} - bool empty() { + void clear() const {} + bool empty() const { return !size(); } // AAA @@ -2064,8 +2066,8 @@ public: throw std::out_of_range("FakeConns::iterator::operator*()"); } } - // std::pair operator->() { return operator*(); } - // const std::pair operator->() const { return operator*(); } + std::pair operator->() { return operator*(); } + const std::pair operator->() const { return operator*(); } const std::pair operator*() const { if (parent->is_legacy()) { auto it = parent->legacy->connections_.begin(); @@ -2145,6 +2147,8 @@ public: throw std::out_of_range("FakeConns::const_iterator::operator*() const"); } } + std::pair operator->() { return operator*(); } + const std::pair operator->() const { return operator*(); } }; const_iterator begin() const { return const_iterator(parent, 0); @@ -2175,7 +2179,7 @@ public: // Canonical tag bool is_legacy() const { - return has_attrs || is_legacy_type(type); + return is_legacy_type(type); }; bool has_memid() { return is_legacy() && legacy->has_memid(); } @@ -2186,7 +2190,7 @@ public: } // TODO stub void set_src_attribute(const std::string &src) { (void)src; }; - bool known () { + bool known () const { return is_legacy() ? legacy->known() : true; } bool input(const RTLIL::IdString &portname) const { @@ -2220,7 +2224,7 @@ public: // TODO is this reasonable at all? const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const; RTLIL::SigSpec &getMutPort(const RTLIL::IdString &portname); - bool hasPort(const RTLIL::IdString &portname) { + bool hasPort(const RTLIL::IdString &portname) const { return connections_.count(portname); } // The need for this function implies setPort will be used on incompat types @@ -2229,7 +2233,7 @@ public: // TODO is this reasonable at all? const RTLIL::Const& getParam(const RTLIL::IdString ¶mname) const; RTLIL::Const& getMutParam(const RTLIL::IdString ¶mname); - bool hasParam(const RTLIL::IdString ¶mname) { + bool hasParam(const RTLIL::IdString ¶mname) const { return parameters.count(paramname); } // The need for this function implies setPort will be used on incompat types diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index ecf0d2c99..ab6c792aa 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -409,7 +409,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons for (auto cell : module->cells()) if (design->selected(module, cell) && cell->type[0] == '$') { if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && - GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1) + GetSize(cell->getPort(ID::B)) == 1 && GetSize(cell->getPort(ID::Y)) == 1) invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A)); if (cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0)) diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc index 51072dd5f..27a83e3ed 100644 --- a/passes/techmap/extractinv.cc +++ b/passes/techmap/extractinv.cc @@ -102,9 +102,9 @@ struct ExtractinvPass : public Pass { if (it2 == cell->parameters.end()) continue; SigSpec sig = port.second; - if (it2->second.size() != sig.size()) + if ((*it2).second.size() != sig.size()) log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", log_id(module->name), log_id(cell->type), log_id(port.first), log_id(param_name)); - RTLIL::Const invmask = it2->second; + RTLIL::Const invmask = (*it2).second; cell->parameters.erase(param_name); if (invmask.is_fully_zero()) continue; diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index e21ec452c..79eb6b6ea 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -345,7 +345,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, if (constmode) { auto conn_list = cell->connections(); - for (auto &conn : conn_list) + for (auto conn : conn_list) { RTLIL::SigSpec sig = conn.second;