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Fix Liberty issue

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This commit is contained in:
Akash Levy 2024-10-03 04:14:20 -07:00
parent dd487ca8a1
commit 654e92e04e
4 changed files with 63 additions and 0 deletions
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5
tests/liberty/liberty_define.lib.verilogsim.ok Normal file
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@ -0,0 +1,5 @@
module not_cell (A, Y);
input A;
output Y;
assign Y = !A[0]; // !A[0]
endmodule