From 654e92e04ef7bc299885da69b47bb935a57e2061 Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Thu, 3 Oct 2024 04:14:20 -0700
Subject: [PATCH] Fix Liberty issue

---
 passes/techmap/libparse.cc                    |  7 +++
 tests/liberty/liberty_define.lib              | 43 +++++++++++++++++++
 tests/liberty/liberty_define.lib.filtered.ok  |  8 ++++
 .../liberty/liberty_define.lib.verilogsim.ok  |  5 +++
 4 files changed, 63 insertions(+)
 create mode 100644 tests/liberty/liberty_define.lib
 create mode 100644 tests/liberty/liberty_define.lib.filtered.ok
 create mode 100644 tests/liberty/liberty_define.lib.verilogsim.ok

diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc
index ebfb325fc..02408da43 100644
--- a/passes/techmap/libparse.cc
+++ b/passes/techmap/libparse.cc
@@ -251,6 +251,13 @@ LibertyAst *LibertyParser::parse()
 			// instead of the ';' too..
 			if ((tok == ';') || (tok == 'n'))
 				break;
+			else if (tok == '[') {
+				while (tok != ']') {
+					tok = lexer(str);
+				}
+				ast->value += '[' + str + ']';
+				continue;
+			}
 			else
 				error();
 			continue;
diff --git a/tests/liberty/liberty_define.lib b/tests/liberty/liberty_define.lib
new file mode 100644
index 000000000..5346283b7
--- /dev/null
+++ b/tests/liberty/liberty_define.lib
@@ -0,0 +1,43 @@
+library (liberty_define) {
+  delay_model : "table_lookup" ;
+  simulation : false ;
+  capacitive_load_unit (1,pF) ;
+  leakage_power_unit : "1pW" ;
+  current_unit : "1A" ;
+  pulling_resistance_unit : "1kohm" ;
+  time_unit : "1ns" ;
+  voltage_unit : "1v" ;
+  library_features : "report_delay_calculation" ;
+  input_threshold_pct_rise : 50 ;
+  input_threshold_pct_fall : 50 ;
+  output_threshold_pct_rise : 50 ;
+  output_threshold_pct_fall : 50 ;
+  slew_lower_threshold_pct_rise : 30 ;
+  slew_lower_threshold_pct_fall : 30 ;
+  slew_upper_threshold_pct_rise : 70 ;
+  slew_upper_threshold_pct_fall : 70 ;
+  slew_derate_from_library : 1.0 ;
+  nom_process : 1.0 ;
+  nom_temperature : 85.0 ;
+  nom_voltage : 0.75 ;
+  type (bus8) {
+    base_type : "array";
+    data_type : "bit";
+    bit_width : 8;
+    bit_from : 7;
+    bit_to : 0;
+  }
+  define (original_pin, pin, string) ;
+  cell (not_cell) {
+    bus (A) {
+      capacitance : 1 ;
+      bus_type : "bus8" ;
+      direction : "input" ;
+    }
+    pin (Y) {
+      function : !A[0] ;
+      direction : "output" ;
+      original_pin : A[0] ;
+    }
+  }
+}
\ No newline at end of file
diff --git a/tests/liberty/liberty_define.lib.filtered.ok b/tests/liberty/liberty_define.lib.filtered.ok
new file mode 100644
index 000000000..d9df6a978
--- /dev/null
+++ b/tests/liberty/liberty_define.lib.filtered.ok
@@ -0,0 +1,8 @@
+library(liberty_define) {
+  cell(not_cell) {
+    pin(Y) {
+      function : !A[0] ;
+      direction : output ;
+    }
+  }
+}
diff --git a/tests/liberty/liberty_define.lib.verilogsim.ok b/tests/liberty/liberty_define.lib.verilogsim.ok
new file mode 100644
index 000000000..292f64425
--- /dev/null
+++ b/tests/liberty/liberty_define.lib.verilogsim.ok
@@ -0,0 +1,5 @@
+module not_cell (A, Y);
+  input A;
+  output Y;
+  assign Y = !A[0]; // !A[0]
+endmodule