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Update to latest and fix all disabled tests
This commit is contained in:
Akash Levy
commit
652a9a63b2
47 changed files with 493 additions and 164 deletions
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@ -1,12 +0,0 @@
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# Various tests
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## Disabled
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- `abc9`: we do not support `abc9`
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- `check`: we do not support memory initialization
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- `ice40_mince_abc9`: we do not support `abc9`
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- `plugin`: we do not support plugins
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## FIXME
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- `cutpoint_blackbox`: unknown issue, needs to be looked into
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@ -1,10 +1,11 @@
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# prefer output name
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design -reset
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read_rtlil <<EOT
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autoidx 2
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module \top
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wire output 3 $y
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wire output 3 \y
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wire input 1 \a
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wire input 2 \b
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cell $and \b_$and_B
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cell $and $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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@ -12,8 +13,193 @@ module \top
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \b
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connect \Y \y
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end
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end
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EOT
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logger -expect log "Rename cell .name in top to y_.and_Y" 1
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logger -expect log "Renamed 1 objects" 1
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debug autoname
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logger -check-expected
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# fallback to shortest name if output is private
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design -reset
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read_rtlil <<EOT
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autoidx 2
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module \top
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wire output 3 $y
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wire input 1 \ab
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wire input 2 \abcd
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cell $or $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \ab
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connect \B \abcd
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connect \Y $y
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end
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end
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EOT
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autoname
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logger -expect log "Rename cell .name in top to ab_.or_A" 1
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logger -expect log "Renamed 1 objects" 1
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debug autoname
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logger -check-expected
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# prefer low fanout over low name length
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design -reset
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read_rtlil <<EOT
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module \top
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wire output 1 $y
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wire input 2 \a
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wire input 3 \bcd
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wire input 4 \c_has_a_long_name
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cell $and $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \bcd
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connect \Y $y
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end
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cell $or $name2
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \c_has_a_long_name
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connect \Y $y
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end
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end
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EOT
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logger -expect log "Rename cell .name in top to bcd_.and_B" 1
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logger -expect log "Rename cell .name2 in top to c_has_a_long_name_.or_B" 1
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logger -expect log "Renamed 2 objects" 1
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debug autoname
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logger -check-expected
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# names are unique
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design -reset
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read_rtlil <<EOT
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module \top
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wire output 3 \y
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wire input 1 \a
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wire input 2 \b
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cell $and $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \b
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connect \Y \y
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end
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cell $and $name2
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \b
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connect \Y \y
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end
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end
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EOT
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logger -expect log "Rename cell .name in top to y_.and_Y" 1
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logger -expect log "Rename cell .name2 in top to y_.and_Y_1" 1
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logger -expect log "Renamed 2 objects" 1
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debug autoname
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logger -check-expected
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# wires get autonames too
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design -reset
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read_rtlil <<EOT
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module \top
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wire output 1 $y
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wire input 2 \a
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wire input 3 \bcd
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wire $c
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wire $d
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wire $e
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cell $__unknown $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \bcd
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connect \Y $c
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end
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cell $or \or
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \bcd
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connect \Y $d
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end
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cell $or $name2
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A $c
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connect \B $d
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connect \Y $e
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end
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cell $and $name3
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A $c
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connect \B $e
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connect \Y $y
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end
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end
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EOT
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design -save order_test
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# wires are named for being cell outputs
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logger -expect log "Rename wire .d in top to or_Y" 1
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logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
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logger -expect log "Renamed 2 objects" 1
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debug autoname t:$or
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logger -check-expected
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# $name gets shortest name (otherwise bcd_$__unknown_B)
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logger -expect log "Rename cell .name in top to a_.__unknown_A" 1
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# another output wire
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logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
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logger -expect log "Renamed 4 objects" 1
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debug autoname
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logger -check-expected
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# don't rename prematurely (some objects should be named after $name2)
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design -load order_test
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# $c gets shortest name, since the cell driving it doesn't have known port
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# directions (otherwise a_$__unknown_A_Y)
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logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
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# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A)
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logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
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logger -expect log "Renamed 6 objects" 1
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debug autoname
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logger -check-expected
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@ -67,6 +67,47 @@ select -read cutpoint.gold.sel
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#select -assert-none % %n
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design -load gold
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select -read cutpoint.gate.sel
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select -read cutpoint.gold.sel
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# nothing in gold but not gate
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#select -assert-none % %n
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select -assert-none % %n
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# replacing the blackbox with a verific-style unknown module should work too
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# (note this specific example loses the values of SOME_PARAM which would
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# normally be retained by verific)
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design -load hier
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delete =bb
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read_rtlil << EOT
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attribute \blackbox 1
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module \bb
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parameter \SOME_PARAM 0
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wire inout 3 \o
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wire inout 2 \b
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wire inout 1 \a
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end
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EOT
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cutpoint -blackbox
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check -assert
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# also concatenated signals, and signals between two inout ports
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design -load hier
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delete top =bb
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read_verilog << EOT
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module top(input [1:0] a, b, output [1:0] o);
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wire [1:0] c, d, e;
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bb #(.SOME_PARAM(1)) bb1 (.a ({a[0], e[1]}), .b (b), .o (c));
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bb #(.SOME_PARAM(2)) bb2 (.a ({c[1], a[0]}), .b (c), .o (d));
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wb wb1 (.a (a), .b (b), .o (e));
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some_mod some_inst (.a (c), .b (d), .c (e), .o (o));
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endmodule
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EOT
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read_rtlil << EOT
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attribute \blackbox 1
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module \bb
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parameter \SOME_PARAM 0
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wire inout 3 width 2 \o
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wire inout 2 width 2 \b
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wire inout 1 width 2 \a
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end
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EOT
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cutpoint -blackbox
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check -assert
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