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Update to latest and fix all disabled tests

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This commit is contained in:
Akash Levy 2025-09-28 01:33:08 -07:00
commit 652a9a63b2
47 changed files with 493 additions and 164 deletions
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4
passes/techmap/abc9_exe.cc
View file

@ -181,8 +181,10 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
for (std::string dont_use_cell : dont_use_cells) {
dont_use_args += stringf("-X \"%s\" ", dont_use_cell);
}
bool first_lib = true;
for (std::string liberty_file : liberty_files) {
abc9_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args, liberty_file);
abc9_script += stringf("read_lib %s %s -w \"%s\" ; ", dont_use_args, first_lib ? "" : "-m", liberty_file);
first_lib = false;
}
if (!constr_file.empty())
abc9_script += stringf("read_constr -v \"%s\"; ", constr_file);

1
passes/techmap/abc9_ops.cc
View file

@ -1600,7 +1600,6 @@ static void replace_zbufs(Design *design)
sig[i] = w;
}
}
log("XXX %s -> %s\n", log_signal(cell->getPort(ID::A)), log_signal(sig));
cell->setPort(ID::A, sig);
}

8
passes/techmap/clockgate.cc
View file

@ -85,7 +85,7 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
continue;
}
log_debug("maybe valid icg: %s\n", cell_name.c_str());
log_debug("maybe valid icg: %s\n", cell_name);
ClockGateCell icg_interface;
icg_interface.name = RTLIL::escape_id(cell_name);
@ -162,9 +162,9 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
winning = cost < goal;
if (winning)
log_debug("%s beats %s\n", icg_interface.name.c_str(), icg_to_beat->name.c_str());
log_debug("%s beats %s\n", icg_interface.name, icg_to_beat->name);
} else {
log_debug("%s is the first of its polarity\n", icg_interface.name.c_str());
log_debug("%s is the first of its polarity\n", icg_interface.name);
winning = true;
}
if (winning) {
@ -396,7 +396,7 @@ struct ClockgatePass : public Pass {
if (!it->second.new_net)
continue;
log_debug("Fix up FF %s\n", cell->name.c_str());
log_debug("Fix up FF %s\n", cell->name);
// Now we start messing with the design
ff.has_ce = false;
// Construct the clock gate

12
passes/techmap/dfflibmap.cc
View file

@ -117,11 +117,11 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std
// the next_state variable isn't just a pin name; perhaps this is an enable?
auto helper = LibertyExpression::Lexer(expr);
auto tree = LibertyExpression::parse(helper);
// log_debug("liberty expression:\n%s\n", tree.str().c_str());
// log_debug("liberty expression:\n%s\n", tree.str());
if (tree.kind == LibertyExpression::Kind::EMPTY) {
if (!warned_cells.count(cell_name)) {
log_debug("Invalid expression '%s' in next_state attribute of cell '%s' - skipping.\n", expr.c_str(), cell_name.c_str());
log_debug("Invalid expression '%s' in next_state attribute of cell '%s' - skipping.\n", expr, cell_name);
warned_cells.insert(cell_name);
}
return false;
@ -140,7 +140,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std
// position that gives better diagnostics here.
if (!pin_names.count(ff_output)) {
if (!warned_cells.count(cell_name)) {
log_debug("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not contain ff output '%s' - skipping.\n", expr.c_str(), cell_name.c_str(), ff_output.c_str());
log_debug("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not contain ff output '%s' - skipping.\n", expr, cell_name, ff_output);
warned_cells.insert(cell_name);
}
return false;
@ -189,7 +189,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std
}
if (!warned_cells.count(cell_name)) {
log_debug("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not evaluate to an enable flop - skipping.\n", expr.c_str(), cell_name.c_str());
log_debug("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not evaluate to an enable flop - skipping.\n", expr, cell_name);
warned_cells.insert(cell_name);
}
return false;
@ -225,10 +225,10 @@ static bool parse_pin(const LibertyAst *cell, const LibertyAst *attr, std::strin
For now, we'll simply produce a warning to let the user know something is up.
*/
if (pin_name.find_first_of("^*|&") == std::string::npos) {
log_debug("Malformed liberty file - cannot find pin '%s' in cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str());
log_debug("Malformed liberty file - cannot find pin '%s' in cell '%s' - skipping.\n", pin_name, cell->args[0]);
}
else {
log_debug("Found unsupported expression '%s' in pin attribute of cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str());
log_debug("Found unsupported expression '%s' in pin attribute of cell '%s' - skipping.\n", pin_name, cell->args[0]);
}
return false;

16
passes/techmap/simplemap.cc
View file

@ -27,6 +27,14 @@
USING_YOSYS_NAMESPACE
YOSYS_NAMESPACE_BEGIN
static void transfer_attr (Cell* to, const Cell* from, const IdString& attr) {
if (from->has_attribute(attr))
to->attributes[attr] = from->attributes.at(attr);
}
static void transfer_src (Cell* to, const Cell* from) {
transfer_attr(to, from, ID::src);
}
void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
@ -261,21 +269,21 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
bool is_ne = cell->type.in(ID($ne), ID($nex));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID2_SUFFIX("xor"), max(GetSize(sig_a), GetSize(sig_b))); // SILIMATE: Improve the naming
RTLIL::Cell *xor_cell = module->addXor(NEW_ID2, sig_a, sig_b, xor_out, is_signed, cell->get_src_attribute()); // SILIMATE: Improve the naming
RTLIL::Cell *xor_cell = module->addXor(NEW_ID2, sig_a, sig_b, xor_out, is_signed); // SILIMATE: Improve the naming
xor_cell->attributes = cell->attributes;
simplemap_bitop(module, xor_cell);
module->remove(xor_cell);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID2_SUFFIX("reduce_out")); // SILIMATE: Improve the naming
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID2_SUFFIX("reduce_or"), xor_out, reduce_out, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID2_SUFFIX("reduce_or"), xor_out, reduce_out, false); // SILIMATE: Improve the naming
reduce_cell->attributes = cell->attributes;
simplemap_reduce(module, reduce_cell);
module->remove(reduce_cell);
if (!is_ne) {
RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID2_SUFFIX("not"), reduce_out, sig_y, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID2_SUFFIX("not"), reduce_out, sig_y, false); // SILIMATE: Improve the naming
not_cell->attributes = cell->attributes;
simplemap_lognot(module, not_cell);
simplemap_lognot(module, not_cell);
module->remove(not_cell);
}
}

10
passes/techmap/techmap.cc
View file

@ -592,7 +592,7 @@ struct TechmapWorker
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
}
else
{
@ -601,7 +601,7 @@ struct TechmapWorker
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(cell->type), extmapper_name);
if (extmapper_name == "simplemap") {
if (simplemap_mappers.count(cell->type) == 0)
@ -953,7 +953,7 @@ struct TechmapWorker
module_queue.insert(m);
}
log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(m_name));
cell->type = m_name;
cell->parameters.clear();
}
@ -964,7 +964,7 @@ struct TechmapWorker
log_msg_cache.insert(msg);
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
techmap_module_worker(design, module, cell, tpl);
cell = nullptr;
}
@ -1295,7 +1295,7 @@ struct TechmapPass : public Pass {
std::string maps = "";
for (auto &map : i.second)
maps += stringf(" %s", log_id(map));
log_debug(" %s:%s\n", log_id(i.first), maps.c_str());
log_debug(" %s:%s\n", log_id(i.first), maps);
}
log_debug("\n");