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Update Yosys runtime flags for Verific to remove multi-port memory support

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This commit is contained in:
Akash Levy 2024-05-24 00:26:37 -07:00
parent 66eabb1d2c
commit 6300c491ea
1 changed files with 2 additions and 2 deletions
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4
frontends/verific/verific.cc
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@ -3209,8 +3209,8 @@ struct VerificPass : public Pass {
// Properly respect order of read and write for rams
RuntimeFlags::SetVar("db_change_inplace_ram_blocking_write_before_read", 1);
RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
RuntimeFlags::SetVar("veri_extract_dualport_rams", 1);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 0);
RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
#ifdef VERIFIC_VHDL_SUPPORT