From 6300c491ea04572854a33044268b713137668298 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Fri, 24 May 2024 00:26:37 -0700 Subject: [PATCH] Update Yosys runtime flags for Verific to remove multi-port memory support --- frontends/verific/verific.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index edbdd93ca..412062235 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3209,8 +3209,8 @@ struct VerificPass : public Pass { // Properly respect order of read and write for rams RuntimeFlags::SetVar("db_change_inplace_ram_blocking_write_before_read", 1); - RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); - RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); + RuntimeFlags::SetVar("veri_extract_dualport_rams", 1); + RuntimeFlags::SetVar("veri_extract_multiport_rams", 0); RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); #ifdef VERIFIC_VHDL_SUPPORT