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Merge pull request #14 from alaindargelas/guard_sig_size_sim_val_mismatch

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Pass no_split_complex_ports to hierarchy command
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Akash Levy 2024-10-29 13:53:43 -07:00 • committed by GitHub
commit 62e27f5a31
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5 changed files with 24 additions and 8 deletions
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3
frontends/verific/verific.cc
View file

@ -2938,7 +2938,7 @@ void verific_cleanup()
verific_import_pending = false; verific_import_pending = false;
} }
std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top, bool opt) std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top, bool opt, bool no_split_complex_port)
{ {
verific_sva_fsm_limit = 16; verific_sva_fsm_limit = 16;
@ -2964,6 +2964,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
if (!verific_error_msg.empty()) if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str()); log_error("%s\n", verific_error_msg.c_str());
if (!no_split_complex_port)
for (auto nl : nl_todo) for (auto nl : nl_todo)
nl.second->ChangePortBusStructures(1 /* hierarchical */); nl.second->ChangePortBusStructures(1 /* hierarchical */);

2
frontends/verific/verific.h
View file

@ -27,7 +27,7 @@ YOSYS_NAMESPACE_BEGIN
extern int verific_verbose; extern int verific_verbose;
extern bool verific_import_pending; extern bool verific_import_pending;
extern std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string(), bool opt = true); extern std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string(), bool opt = true, bool no_split_complex_ports = true);
extern pool<int> verific_sva_prims; extern pool<int> verific_sva_prims;

2
passes/cmds/Makefile.inc
View file

@ -51,3 +51,5 @@ OBJS += passes/cmds/dft_tag.o
OBJS += passes/cmds/future.o OBJS += passes/cmds/future.o
OBJS += passes/cmds/box_derive.o OBJS += passes/cmds/box_derive.o
OBJS += passes/cmds/example_dt.o OBJS += passes/cmds/example_dt.o
OBJS += passes/cmds/activity.o
OBJS += passes/cmds/splitnetlist.o

5
passes/cmds/activity.cc
View file

@ -77,8 +77,13 @@ struct ActivityProp {
// Assign them to each SigBit (1 signal bit) // Assign them to each SigBit (1 signal bit)
for (int i = 0; i < GetSize(sig); i++) { for (int i = 0; i < GetSize(sig); i++) {
SigBit bit(sig[i]); SigBit bit(sig[i]);
if (i < activities.size() -1) {
ActivityMap.emplace(bit, activities[i]); ActivityMap.emplace(bit, activities[i]);
DutyMap.emplace(bit, duties[i]); DutyMap.emplace(bit, duties[i]);
} else {
ActivityMap.emplace(bit, "0.0");
DutyMap.emplace(bit, "0.0");
}
} }
} }
// Attach port activity to cell using sigmap // Attach port activity to cell using sigmap

12
passes/hierarchy/hierarchy.cc
View file

@ -797,6 +797,9 @@ struct HierarchyPass : public Pass {
log(" -opt\n"); log(" -opt\n");
log(" optimize all modules in design hierarchy.\n"); log(" optimize all modules in design hierarchy.\n");
log("\n"); log("\n");
log(" -no_split_complex_ports\n");
log(" Complex ports (structs or arrays) are not split and remain packed as a single port.\n");
log("\n");
log(" -chparam name value \n"); log(" -chparam name value \n");
log(" elaborate the top module using this parameter value. Modules on which\n"); log(" elaborate the top module using this parameter value. Modules on which\n");
log(" this parameter does not exist may cause a warning message to be output.\n"); log(" this parameter does not exist may cause a warning message to be output.\n");
@ -825,6 +828,7 @@ struct HierarchyPass : public Pass {
log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n"); log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n");
bool flag_opt = false; bool flag_opt = false;
bool flag_no_split_complex_ports = false;
bool flag_check = false; bool flag_check = false;
bool flag_simcheck = false; bool flag_simcheck = false;
bool flag_smtcheck = false; bool flag_smtcheck = false;
@ -940,6 +944,10 @@ struct HierarchyPass : public Pass {
flag_opt = true; flag_opt = true;
continue; continue;
} }
if (args[argidx] == "-no_split_complex_ports") {
flag_no_split_complex_ports = true;
continue;
}
if (args[argidx] == "-chparam" && argidx+2 < args.size()) { if (args[argidx] == "-chparam" && argidx+2 < args.size()) {
const std::string &key = args[++argidx]; const std::string &key = args[++argidx];
const std::string &value = args[++argidx]; const std::string &value = args[++argidx];
@ -989,7 +997,7 @@ struct HierarchyPass : public Pass {
if (top_mod == nullptr && !load_top_mod.empty()) { if (top_mod == nullptr && !load_top_mod.empty()) {
#ifdef YOSYS_ENABLE_VERIFIC #ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending) { if (verific_import_pending) {
load_top_mod = verific_import(design, parameters, load_top_mod, flag_opt); load_top_mod = verific_import(design, parameters, load_top_mod, flag_opt, flag_no_split_complex_ports);
top_mod = design->module(RTLIL::escape_id(load_top_mod)); top_mod = design->module(RTLIL::escape_id(load_top_mod));
} }
#endif #endif
@ -998,7 +1006,7 @@ struct HierarchyPass : public Pass {
} else { } else {
#ifdef YOSYS_ENABLE_VERIFIC #ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending) if (verific_import_pending)
verific_import(design, parameters, std::string(), flag_opt); verific_import(design, parameters, std::string(), flag_opt, flag_no_split_complex_ports);
#endif #endif
} }