From 667a07ab56d01aaa1e16ac7e8efb0597eaa66c98 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 29 Oct 2024 10:39:21 -0700 Subject: [PATCH 1/5] Guard against sig mismatch --- passes/cmds/Makefile.inc | 2 ++ passes/cmds/activity.cc | 9 +++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 49a790f67..5d9d08481 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -51,3 +51,5 @@ OBJS += passes/cmds/dft_tag.o OBJS += passes/cmds/future.o OBJS += passes/cmds/box_derive.o OBJS += passes/cmds/example_dt.o +OBJS += passes/cmds/activity.o +OBJS += passes/cmds/splitnetlist.o \ No newline at end of file diff --git a/passes/cmds/activity.cc b/passes/cmds/activity.cc index 2940bad2a..73a1520d0 100644 --- a/passes/cmds/activity.cc +++ b/passes/cmds/activity.cc @@ -77,8 +77,13 @@ struct ActivityProp { // Assign them to each SigBit (1 signal bit) for (int i = 0; i < GetSize(sig); i++) { SigBit bit(sig[i]); - ActivityMap.emplace(bit, activities[i]); - DutyMap.emplace(bit, duties[i]); + if (i < activities.size() -1) { + ActivityMap.emplace(bit, activities[i]); + DutyMap.emplace(bit, duties[i]); + } else { + ActivityMap.emplace(bit, "0.0"); + DutyMap.emplace(bit, "0.0"); + } } } // Attach port activity to cell using sigmap From 3e4964a0e44a4af1ce58200cefd9c34dbb9cd182 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 29 Oct 2024 10:40:20 -0700 Subject: [PATCH 2/5] Guard against sig mismatch --- passes/cmds/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 5d9d08481..2fde35346 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -52,4 +52,4 @@ OBJS += passes/cmds/future.o OBJS += passes/cmds/box_derive.o OBJS += passes/cmds/example_dt.o OBJS += passes/cmds/activity.o -OBJS += passes/cmds/splitnetlist.o \ No newline at end of file +OBJS += passes/cmds/splitnetlist.o From cad46d9c6662ba9eca66abc67f474f5f3d5e5247 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 29 Oct 2024 10:44:16 -0700 Subject: [PATCH 3/5] formating --- passes/cmds/activity.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/cmds/activity.cc b/passes/cmds/activity.cc index 73a1520d0..2449f37c4 100644 --- a/passes/cmds/activity.cc +++ b/passes/cmds/activity.cc @@ -78,11 +78,11 @@ struct ActivityProp { for (int i = 0; i < GetSize(sig); i++) { SigBit bit(sig[i]); if (i < activities.size() -1) { - ActivityMap.emplace(bit, activities[i]); - DutyMap.emplace(bit, duties[i]); + ActivityMap.emplace(bit, activities[i]); + DutyMap.emplace(bit, duties[i]); } else { ActivityMap.emplace(bit, "0.0"); - DutyMap.emplace(bit, "0.0"); + DutyMap.emplace(bit, "0.0"); } } } From 615f523ef41d1b1c87dad8775e7273f6990daa58 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 29 Oct 2024 13:37:03 -0700 Subject: [PATCH 4/5] pass no_split_complex_ports to hierarchy command --- frontends/verific/verific.cc | 7 ++++--- frontends/verific/verific.h | 2 +- passes/hierarchy/hierarchy.cc | 9 +++++++-- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9c7b6d937..56f3fcf31 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2938,7 +2938,7 @@ void verific_cleanup() verific_import_pending = false; } -std::string verific_import(Design *design, const std::map ¶meters, std::string top, bool opt) +std::string verific_import(Design *design, const std::map ¶meters, std::string top, bool opt, bool no_split_complex_port) { verific_sva_fsm_limit = 16; @@ -2964,8 +2964,9 @@ std::string verific_import(Design *design, const std::mapChangePortBusStructures(1 /* hierarchical */); + if (!no_split_complex_port) + for (auto nl : nl_todo) + nl.second->ChangePortBusStructures(1 /* hierarchical */); VerificExtNets worker; for (auto nl : nl_todo) diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 77d9c3e6e..65c3bfb7c 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -27,7 +27,7 @@ YOSYS_NAMESPACE_BEGIN extern int verific_verbose; extern bool verific_import_pending; -extern std::string verific_import(Design *design, const std::map ¶meters, std::string top = std::string(), bool opt = true); +extern std::string verific_import(Design *design, const std::map ¶meters, std::string top = std::string(), bool opt = true, bool no_split_complex_ports = true); extern pool verific_sva_prims; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index aeb748b3c..641eb7d7f 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -825,6 +825,7 @@ struct HierarchyPass : public Pass { log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n"); bool flag_opt = false; + bool flag_no_split_complex_ports = false; bool flag_check = false; bool flag_simcheck = false; bool flag_smtcheck = false; @@ -940,6 +941,10 @@ struct HierarchyPass : public Pass { flag_opt = true; continue; } + if (args[argidx] == "-no_split_complex_ports") { + flag_no_split_complex_ports = true; + continue; + } if (args[argidx] == "-chparam" && argidx+2 < args.size()) { const std::string &key = args[++argidx]; const std::string &value = args[++argidx]; @@ -989,7 +994,7 @@ struct HierarchyPass : public Pass { if (top_mod == nullptr && !load_top_mod.empty()) { #ifdef YOSYS_ENABLE_VERIFIC if (verific_import_pending) { - load_top_mod = verific_import(design, parameters, load_top_mod, flag_opt); + load_top_mod = verific_import(design, parameters, load_top_mod, flag_opt, flag_no_split_complex_ports); top_mod = design->module(RTLIL::escape_id(load_top_mod)); } #endif @@ -998,7 +1003,7 @@ struct HierarchyPass : public Pass { } else { #ifdef YOSYS_ENABLE_VERIFIC if (verific_import_pending) - verific_import(design, parameters, std::string(), flag_opt); + verific_import(design, parameters, std::string(), flag_opt, flag_no_split_complex_ports); #endif } From 4dd26490c2ca51722c143a5f868528c671cd8222 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 29 Oct 2024 13:52:46 -0700 Subject: [PATCH 5/5] help message --- passes/hierarchy/hierarchy.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 641eb7d7f..00df6e1d6 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -797,6 +797,9 @@ struct HierarchyPass : public Pass { log(" -opt\n"); log(" optimize all modules in design hierarchy.\n"); log("\n"); + log(" -no_split_complex_ports\n"); + log(" Complex ports (structs or arrays) are not split and remain packed as a single port.\n"); + log("\n"); log(" -chparam name value \n"); log(" elaborate the top module using this parameter value. Modules on which\n"); log(" this parameter does not exist may cause a warning message to be output.\n");