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smt2 backend produces verilog testbench which errors out with Verilator; genclock is defined twice. This patch removes the redefinition of genclock.

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trayres 2025-05-14 10:05:07 -07:00
parent e3ae7b1400
commit 62b29b0b75
1 changed files with 0 additions and 1 deletions
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backends/smt2/smtbmc.py
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@ -1161,7 +1161,6 @@ def write_vlogtb_trace(steps, index):
print(" initial genclock = 1;", file=f)
print("`endif", file=f)
print(" reg genclock = 1;", file=f)
print(" reg [31:0] cycle = 0;", file=f)
primary_inputs = list()