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smt2 backend produces verilog testbench which errors out with Verilator; genclock is defined twice. This patch removes the redefinition of genclock.
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@ -1161,7 +1161,6 @@ def write_vlogtb_trace(steps, index):
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print(" initial genclock = 1;", file=f)
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print("`endif", file=f)
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print(" reg genclock = 1;", file=f)
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print(" reg [31:0] cycle = 0;", file=f)
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primary_inputs = list()
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